Staff

Dr.-Ing. Jürgen Röber (Akad. Rat)

About Jürgen Röber

Biography

2007-2010: B.Sc. in Electrical Engineering
2010-2013: M.Sc. in Systems of Information and Multimedia Technology
2013-2016: PhD Student with finished degree Dr.-Ing. in Electrical Engineering
Since 2015: Head of the team Mixed Signal Integrated Circuits (MXIC)

Areas of Interest

  • Analog IC Design
  • Mixed Signal IC Design
  • Mixed Signal System Design
  • RF Front-End Design for digital satellite radio broadcasting

Publications

2020

  • M. Frank, F. Lurz, M. Kempf, J. Röber, R. Weigel, and A. Koelpin, "Miniaturized Ultra-Wideband Antenna Design for Human Implants" in IEEE Radio & Wireless Week 2020, San Antonio, Texas, USA, 2020, pp. 48-51. [DOI] [Bibtex]
    @inproceedings{frank2020,
    author = {Frank, Martin and Lurz, Fabian and Kempf, Markus and Röber, Jürgen and Weigel, Robert and Koelpin, Alexander},
    language = {English},
    booktitle = {IEEE Radio & Wireless Week 2020},
    cris = {https://cris.fau.de/converis/publicweb/publication/226710795},
    year = {2020},
    month = {01},
    day = {26},
    doi = {10.1109/RWS45077.2020.9050119},
    eventdate = {2020-01-26/2020-01-29},
    faupublication = {yes},
    pages = {48--51},
    peerreviewed = {Yes},
    title = {Miniaturized Ultra-Wideband Antenna Design for Human Implants},
    type = {Konferenzschrift},
    venue = {San Antonio, Texas, USA},
    }

2019

  • M. Kempf, J. Röber, F. Ohnhäuser, and R. Weigel, "A 12 GHz all-digital PLL with linearized chirps for FMCW Radar" in 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, 2019, pp. 482-485. [DOI] [Bibtex]
    @inproceedings{kempf2019,
    abstract = {An accumulator based all-digital PLL for linear FMCW chirp generation is proposed. Operating at a Reference Frequency of 128 MHz the Phase Noise at 100 kHz offset measures -80 dBc/Hz. The proposed chirp linearization scheme allows for a wide range of chirp periods from 40 us up to 200 ms with an RMS Frequency Error of down to 7.26 kHz for slow and 882 kHz for fast chirps. Without dithering, the digitally, switched capacitor controlled oscillator presented in this work achieves an average step size of below 25 kHz while ranging from 11.596 GHz to 12.783 GHz.},
    author = {Kempf, Markus and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert},
    publisher = {Institute of Electrical and Electronics Engineers Inc.},
    booktitle = {2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019},
    cris = {https://cris.fau.de/converis/publicweb/publication/234624376},
    year = {2019},
    month = {11},
    day = {01},
    doi = {10.1109/ICECS46596.2019.8965077},
    eventdate = {2019-11-27/2019-11-29},
    eventtitle = {26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019},
    faupublication = {yes},
    isbn = {9781728109961},
    keywords = {All-Digital Phase Locked Loops; Chirp Linearization; FMCW Radar; Frequency Synthesis},
    pages = {482--485},
    peerreviewed = {unknown},
    title = {A 12 GHz all-digital PLL with linearized chirps for FMCW Radar},
    venue = {Genoa, Italy},
    }
  • T. Reißland, M. Kuba, J. Röber, A. Koelpin, R. Weigel, and F. Lurz, "Synchronization approaches and improvements for a low-complexity power line communication system" in 2019 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids, SmartGridComm 2019, Beijing, China, 2019. [DOI] [Bibtex]
    @inproceedings{reissland2019d,
    abstract = {This paper presents several improvements of the energy-pattern based sequence detection (EPSD) algorithm for FSK-based single-phase power line communication (PLC) systems, in terms of complexity, reliability and synchronization. A time synchronization is presented which fulfills the well known task of synchronizing transmitter and receiver, but also helps to avoid transmissions in periods of rough noise conditions. The synchronization method is based on a maximum-likelihood approach that makes use of the phase of the mains voltage. Further improvements concern the codes used for the trans-mitted sequences as well as the combination of the information within both FSK carrier-frequencies in terms of equal gain and maximum ratio combining. Additionally an approach for a low-complexity frame synchronization is presented.},
    author = {Reißland, Torsten and Kuba, Matthias and Röber, Jürgen and Koelpin, Alexander and Weigel, Robert and Lurz, Fabian},
    publisher = {Institute of Electrical and Electronics Engineers Inc.},
    booktitle = {2019 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids, SmartGridComm 2019},
    cris = {https://cris.fau.de/converis/publicweb/publication/230837657},
    year = {2019},
    month = {10},
    day = {01},
    doi = {10.1109/SMARTGRIDCOMM.2019.8909724},
    eventdate = {2019-10-21/2019-10-23},
    eventtitle = {2019 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids, SmartGridComm 2019},
    faupublication = {yes},
    isbn = {9781538680995},
    keywords = {Fsk; Low-power; Plc; Wakeup receiver},
    peerreviewed = {unknown},
    title = {Synchronization approaches and improvements for a low-complexity power line communication system},
    venue = {Beijing, China},
    }
  • D. Schuklin, J. Röber, M. Stadelmayer, T. Mai, R. Weigel, and A. Hagelauer, "Highly Integrated Low Power Photomultiplier Readout ASIC Comprising Fast ADC to Be Used in the Antarctic Ice" in 2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Orlando, Florida, USA, 2019. [Bibtex]
    @inproceedings{schuklin2019,
    abstract = {After the successful launch of IceCube, the work is currently concentrated the next generation neutrino observatory at South Pole, IceCube Gen2. The neutrino detection and post processing accuracy mostly relies on used electronic hardware. The proposed highly integrated, low power photomultiplier readout ASIC is designed for function in low temperatures of Antarctic. The microchip comprises an input pre-amplifier, a clock generator and an ADC with encoder logic featuring sampling rate of 500MHz, 6bit output accuracy with a smart extension of input related resolution up to 8bit in the area of interest. It achieves the same accuracy like a standard 8bit ADC architecture but with significantly less hardware overhead and power dissipation.
    }, author = {Schuklin, Dennis and Röber, Jürgen and Stadelmayer, Markus and Mai, Timo and Weigel, Robert and Hagelauer, Amelie}, language = {English}, booktitle = {2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)}, cris = {https://cris.fau.de/converis/publicweb/publication/208580332}, year = {2019}, month = {02}, day = {20}, eventdate = {2019-01-20/2019-01-23}, faupublication = {yes}, peerreviewed = {unknown}, title = {Highly Integrated Low Power Photomultiplier Readout ASIC Comprising Fast ADC to Be Used in the Antarctic Ice}, type = {Konferenzschrift}, venue = {Orlando, Florida, USA}, }

2018

  • C. Söll, M. Reichenbach, J. Röber, A. Hagelauer, R. Weigel, and D. Fey, "Case Study on Memristor-Based Multilevel Memories", International Journal of Circuit Theory and Applications, vol. 46, iss. 1, pp. 99-112, 2018. [DOI] [Bibtex]
    @article{soell2017,
    abstract = {In this work, the benefits of memristor-based multilevel memories are described along with their design problems. Starting with measurements of discrete actual devices, a discrete memristor based multilevel memory is developed. It uses a printed circuit board in order to connect eight packaged memristors from Bio Inspired to test a ternary Arithmetic Logic Unit (ALU) on a field programmable gate array (FPGA). These circuits are then integrated in the second proposed memory system based on a 150nm CMOS process that can be equipped with memristors on top of the metal layers. This integrated solution includes proper read-out, erase and write circuits to control real memristors, and 32x32 memristive memory cells. It is compared to a common static random-access memory (SRAM) in terms of area, computation speed and power consumption showing benefits for memory sizes bigger than 70 words. Since yield and device variations are still a big issue in memristor fabrication, methods to counter these problems are also proposed in the end. An actual implementation should offer several trimming solutions to ensure proper functionality of a prototype memory as well as a power-on calibration, until these problems are solved. The development of the presented memories is not only based on different models but also measurements done with real devices.},
    author = {Söll, Christopher and Reichenbach, Marc and Röber, Jürgen and Hagelauer, Amelie and Weigel, Robert and Fey, Dietmar},
    publisher = {Wiley Online Library},
    cris = {https://cris.fau.de/converis/publicweb/publication/108239824},
    year = {2018},
    month = {01},
    doi = {10.1002/CTA.2379},
    faupublication = {yes},
    issn = {0098-9886},
    journaltitle = {International Journal of Circuit Theory and Applications},
    keywords = {Memristor; Multi-Level Memory; Memory Interface; Memristive Computing; GRK-1773},
    number = {1},
    pages = {99--112},
    peerreviewed = {Yes},
    shortjournal = {INT J CIRC THEOR APP},
    title = {Case Study on Memristor-Based Multilevel Memories},
    type = {Article in Journal},
    volume = {46},
    }

2017

  • T. Mai, K. Schmid, A. Hagelauer, R. Weigel, and J. Röber, "A fully-differential Operational Amplifier using a new Chopping Technique and Low-Voltage Input Devices" in 24th IEEE International Conference on Electronics, Circuits and Systems, Batumi, Georgia, 2017, pp. 74-77. [DOI] [Bibtex]
    @inproceedings{mai2017,
    abstract = {A fully differential CMOS operational amplifier is presented. It uses a new chopping technique that works without the use of switching transistors in the high gain path, resulting in high noise performance and low offset. It is designed in a low-cost 180 nm process with a 5V supply voltage. In critical places, such as the differential pair, 1.8V-devices are used, as they provide much better matching and noise performance, and at the same time have lower parasitics. They are protected from breakdown conditions by several circuit techniques. Some of them are described below. The operational amplifier is used in a differential programmable gain amplifier for processing signals of up to 50 kHz bandwith with a SINAD > 100 dB, making it suitable as a preamplifier for 18-Bit ADCs.},
    author = {Mai, Timo and Schmid, Konstantin and Hagelauer, Amelie and Weigel, Robert and Röber, Jürgen},
    language = {English},
    booktitle = {24th IEEE International Conference on Electronics, Circuits and Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/108861104},
    year = {2017},
    month = {12},
    day = {05},
    doi = {10.1109/ICECS.2017.8292081},
    eventdate = {2017-12-05/2017-12-08},
    faupublication = {yes},
    keywords = {chopping; operational amplifier; gain boosting; 1/f-noise; offset; programmable gain amplifier;},
    pages = {74--77},
    peerreviewed = {unknown},
    title = {A fully-differential Operational Amplifier using a new Chopping Technique and Low-Voltage Input Devices},
    type = {Journal Article},
    venue = {Batumi, Georgia},
    }
  • R. Löhr, L. Bender, J. Röber, F. Ohnhäuser, and R. Weigel, "Analysis of the Settling Behavior of an External Reference Voltage Source for a 16 Bit and 200 MS/s Pipeline Analog-to-Digital Converter" in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgien, Georgia, 2017. [Bibtex]
    @inproceedings{loehr2017a,
    abstract = {
    High-Performance Analog to Digital Converter (ADC) have high requirements concerning the reference voltage source. In a small period of time the reference voltage has to settle with a high accuracy. Otherwise the linearity of the ADC degrades. In this paper the settling of an external reference voltage source is examined. Therefore optimization techniques for the signal path of the reference voltage are presented. This includes methods for reducing the external parasitic inductanceas well as design techniques for an enhanced settling curve. Under typical conditions, the achieved reference voltage source settles with an accuracy of 15 uV in less than halve a clock cycle for a 200 MS/s and 16 bits Pipeline ADC.
    }, author = {Löhr, Robert and Bender, Leon and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert}, language = {English}, booktitle = {24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, cris = {https://cris.fau.de/converis/publicweb/publication/119647484}, year = {2017}, month = {12}, day = {08}, eventdate = {2017-12-04/2017-12-08}, faupublication = {yes}, keywords = {reference voltage; settling; Pipeline ADC; external parasitic inductance; attenuation}, peerreviewed = {unknown}, title = {Analysis of the Settling Behavior of an External Reference Voltage Source for a 16 Bit and 200 MS/s Pipeline Analog-to-Digital Converter}, type = {Konferenzschrift}, venue = {Batumi, Georgien, Georgia}, }
  • R. Löhr, M. Stadelmayer, J. Röber, F. Ohnhäuser, and R. Weigel, "A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter" in ECCTD, Italien, 2017. [Bibtex]
    @inproceedings{loehr2017,
    abstract = {
    High-Performance Analog-to-Digital Converter
    (ADC) have high requirements concerning sampling rate and
    linearity. Therefore a new formula is derived to determine,
    which pipeline stage dependent on the used capacitor sizes
    needs to be calibrated for the targeted linearity. Furthermore,
    a model of a 16 bit and 200MS/s pipeline ADC is described. A
    combination of a digital foreground and a digital background
    calibration is presented, which can compensate linear errors
    and achieves a DNL smaller than ±1 and a THD of -88 dB.
    }, author = {Löhr, Robert and Stadelmayer, Markus and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert}, language = {English}, publisher = {IEEE}, booktitle = {ECCTD}, cris = {https://cris.fau.de/converis/publicweb/publication/106860204}, year = {2017}, month = {07}, faupublication = {yes}, keywords = {Pipeline ADC,modeling,common mode jump,capacitor-flip-over architecture,digital calibration,foreground,background,high resolution.}, peerreviewed = {unknown}, title = {A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter}, venue = {Italien}, }
  • C. Söll, J. Röber, H. Milosiu, R. Weigel, and A. Hagelauer, "Area-Efficient Fully Integrated Dual-Band Class-E/F Power Amplifier with Switchable Output Power for a BPSK/OOK Transmitter" in IEEE International Symposium on Circuits and Systems, Baltimore, USA, 2017, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{soell2017a,
    abstract = {This paper presents a novel area-efficient dual-band class-E/F power amplifier (PA) with switchable output power. It is targeted to work in a BPSK/OOK transmitter in smart facility applications like an autarkic asset-tracking system based on small sensor nodes. The amplifier is able to operate at both 434MHz and 868MHz without the need for additional inductors. The output power settings at 868MHz are controllable between -1.79dBm and -24.61dBm at 4.96mA and 1.43mA current consumption, respectively. The whole circuit including all inductors and the matching network in front of the antenna consumes only 0.9mm2 chip area and is fully integrated in a 180nm CMOS process together with a VCO and a PLL.},
    author = {Söll, Christopher and Röber, Jürgen and Milosiu, Heinrich and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {IEEE International Symposium on Circuits and Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/108242684},
    year = {2017},
    doi = {10.1109/ISCAS.2017.8050676},
    faupublication = {yes},
    keywords = {Class-E/F Power Amplifier; Dual-Band; Switchable Output Power; Asset-Tracking System},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Area-Efficient Fully Integrated Dual-Band Class-E/F Power Amplifier with Switchable Output Power for a BPSK/OOK Transmitter},
    type = {Konferenzschrift},
    venue = {Baltimore, USA},
    }

2016

  • D. Schuklin, D. Hohnloser, T. Lieske, M. Reichenbach, A. Bänisch, B. Pfundt, J. Röber, R. Weigel, and D. Fey, "Systemkonzept eines autarken und intelligenten Miniatur-Sensors für Smart Home" in VDE Kongress 2016: Internet der Dinge, 2016. [Bibtex]
    @inproceedings{shuklin2016,
    abstract = {Trotz der erheblichen Fortschritte im Bereich Smart Home, stellt die Installation von Hunderten von Sensoren eine der größten Herausforderungen dar. Eine mögliche Lösung für dieses Problem ist die Integration aller Komponenten innerhalb einer integrierten Schaltung. Dieser Beitrag stellt ein Konzept für ein intelligentes Sensorsystem dar, welches die wichtigsten Sensoren für das intelligente Zuhause (wie z.B. Drucksensor, Gassensor, Temperatur-, oder Lichtsensor) auf einem Chip vereint. Dadurch wird das Messen von lokalen Temperaturen, Lichtverhältnissen, Drucks und sogar Luftqualität ermöglicht. Mit diesen umfassenden Informationen können lebensunterstützende Systeme, Einbruchsdetektion, automatisierte Klimaregelung und Beleuchtungssteuerung in Räumen und vieles mehr realisiert werden. Langfristiges Ziel dieser Arbeit ist die Entwicklung eines selbst organisierenden und autonomen Netzwerks von intelligenten Sensoren im Bereich Smart Home. Mit Abmessungen von wenigen Zentimetern, kann jeder Sensor nahezu überall angebracht werden, wie zum Beispiel an einem Fenster.},
    author = {Schuklin, Dennis and Hohnloser, Daniel and Lieske, Tobias and Reichenbach, Marc and Bänisch, Andreas and Pfundt, Benjamin and Röber, Jürgen and Weigel, Robert and Fey, Dietmar},
    booktitle = {VDE Kongress 2016: Internet der Dinge},
    cris = {https://cris.fau.de/converis/publicweb/publication/119421544},
    year = {2016},
    month = {11},
    eventtitle = {VDE Kongress 2016: Internet der Dinge},
    faupublication = {yes},
    keywords = {Smart Home; Intelligent Sensor System; MEMS Sensor; Analog to Digital Converter; Digital Processing Unit},
    peerreviewed = {Yes},
    title = {Systemkonzept eines autarken und intelligenten Miniatur-Sensors für Smart Home},
    }
  • J. Röber, "In CMOS integriertes Mehrantennen-Diversity-Empfangssystem für digitales Satellitenradio", 2016. [Bibtex]
    @phdthesis{roeber2016a,
    author = {Röber, Jürgen},
    institution = {FAU Erlangen-Nürnberg},
    language = {German},
    publisher = {FAU University Press},
    cris = {https://cris.fau.de/converis/publicweb/publication/119755724},
    year = {2016},
    month = {11},
    day = {21},
    entrysubtype = {Dissertation},
    faupublication = {yes},
    isbn = {9783944057934},
    peerreviewed = {automatic},
    title = {In CMOS integriertes Mehrantennen-Diversity-Empfangssystem für digitales Satellitenradio},
    type = {Dissertation},
    }
  • D. Fey, M. Reichenbach, C. Söll, M. Biglari, J. Röber, and R. Weigel, "Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits" in Proceedings of the Second International Symposium on Memory Systems, Alexandria, VA, USA, 2016, pp. 442-454. [DOI] [Bibtex]
    @inproceedings{fey2016a,
    abstract = {

    Signed-digit (SD) arithmetic exploits positive and negative digits requiring more than two states. It is long known that an addition using trits, i.e. each digit stores not only a 0 or a 1 but also either 2 or -1, requires only a constant number of steps independent of the operands' word length. However, current processors could not profit from that due to the lack of fast, dense and CMOS compatible memory cells that can store reliably multiple states. Memristors offer these features making it necessary to re-evaluate different SD number representations and to evaluate the consequences of an implementation of a multi-value register file with memristors concerning latency, area and energy consumption.

    Using memristors as multi-value register reduces latency and area on one side compared to flip-flop based memories. On the other side this requires additional sophisticated control circuitry to implement ADCs/DACs, current limiting circuits and to generate control signals to read, write and erase memristors. The paper determines the break-even points at which ternary circuits attached to memristor based registers show better energy-delay products and less area consumption and how much power consumption these improvements cost. By layout synthesis is shown that ternary adders with trit-storing memristors can reduce the latency for a word length of 16 digits about 19% and about 52% for 512 digits compared to a binary carry-look-ahead (CLA) adder with nearly the same power consumption.

    }, author = {Fey, Dietmar and Reichenbach, Marc and Söll, Christopher and Biglari, Mehrdad and Röber, Jürgen and Weigel, Robert}, language = {English}, publisher = {ACM}, booktitle = {Proceedings of the Second International Symposium on Memory Systems}, cris = {https://cris.fau.de/converis/publicweb/publication/108131584}, year = {2016}, month = {10}, day = {03}, doi = {10.1145/2989081.2989124}, eventdate = {2016-10-03/2016-10-06}, eventtitle = {The International Symposium on Memory Systems (MEMSYS)}, faupublication = {yes}, isbn = {9781450343053}, keywords = {Signed-digit arithmetic multi-bit memristors memristive computing; multi-bit memristors; memristive computing; GRK}, pages = {442--454}, peerreviewed = {Yes}, title = {Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits}, type = {Journal Article}, url = {https://dl.acm.org/citation.cfm?id=2989124}, venue = {Alexandria, VA, USA}, }
  • S. Senega, J. Röber, A. Nassar, R. Weigel, C. Heuer, and S. Lindenmeier, "Compact Scan-Phase Antenna Diversity Related System Considerations" in European Microwave Week, London, 2016, p. 4. [Bibtex]
    @inproceedings{senega2016,
    abstract = {An integrated antenna diversity system is described which enables a high increase of reception performance for satellite digital audio radio services (SDARS). A detailed analysis is given for the gain and noise figure requirements specifically regarding the implementation in an integrated circuit. In this contribution a compact integrated diversity system is specified and its realization is described. Also sufficient immunity to high level interferers must be ensured which can be in close proximity as far as frequency distance is concerned. On base of the specified values the system provides an overall gain of 26.8 dB with a noise figure of 0.84 dB including the single rf cable connecting the diversity antenna set to the unmodified standard SDARS receiver. A hardware demonstrator of our scan-phase antenna diversity system is presented in which the phase aligned rf combining and signal selection is implemented in a compact IC with a package size of only 8mm by 8 mm. Measurement results with recorded Rayleigh fading signals from a test drive in the US with a duration of 290 s show a reduction of audio mutes from 29.8 s of the best single antenna to only 4.1 s with our scan-phase antenna diversity demonstrator.},
    author = {Senega, Simon and Röber, Jürgen and Nassar, Ali and Weigel, Robert and Heuer, Christian and Lindenmeier, Stefan},
    publisher = {IEEE},
    booktitle = {European Microwave Week},
    cris = {https://cris.fau.de/converis/publicweb/publication/124158804},
    year = {2016},
    month = {10},
    eventtitle = {European Microwave Week},
    faupublication = {yes},
    pages = {4},
    peerreviewed = {Yes},
    title = {Compact Scan-Phase Antenna Diversity Related System Considerations},
    venue = {London},
    }
  • L. Shi, M. Berger, B. Bier, C. Söll, J. Röber, R. Fahrig, B. Eskofier, A. Maier, and J. Maier, "Analog Non-Linear Transformation-Based Tone Mapping for Image Enhancement in C-arm CT" in IEEE Medical Imaging Conference (MIC), Strasbourg, France, 2016. [Bibtex]
    @inproceedings{shi2016a,
    abstract = {Flat-Panel C-arm Computed Tomography (CT) suffers from pixel saturation due to the detector’s limited dynamic range. We describe a novel approach to analog, non-linear tone mapping (TM) for preventing detector saturation. An analog TM operator (TMO) applies a non-linear transformation in a CMOS sensor and its inverse TMO based on 14-bit digital raw data. This is done in order to prevent overexposure and to enhance image quality to 32 bits. The method was applied to the cases of low-contrast head imaging and to that of imaging both knees. Cone-beam projection data with and without overexposure was simulated for a 200° short-scan of the knees and a 360° full-scan of a Forbild head phantom. The results show an increased correlation coefficient of 0.99 compared to 0.96 for overexposed knee data and a higher low-contrast visibility (CC=0.99) compared to linear quantization (CC=0.97).},
    author = {Shi, Lan and Berger, Martin and Bier, Bastian and Söll, Christopher and Röber, Jürgen and Fahrig, Rebecca and Eskofier, Björn and Maier, Andreas and Maier, Jennifer},
    booktitle = {IEEE Medical Imaging Conference (MIC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/109689624},
    year = {2016},
    month = {10},
    faupublication = {yes},
    keywords = {GRK-1773},
    peerreviewed = {Yes},
    title = {Analog Non-Linear Transformation-Based Tone Mapping for Image Enhancement in C-arm CT},
    venue = {Strasbourg, France},
    }
  • C. Söll, L. Shi, J. Röber, M. Reichenbach, R. Weigel, and A. Hagelauer, "Low-Power Analog Smart Camera Sensor for Edge Detection" in IEEE International Conference on Image Processing (ICIP), Phoenix, USA, 2016. [DOI] [Bibtex]
    @inproceedings{soell2016,
    abstract = {This work presents an intelligent analog image sensor system for smart camera applications with the need of edge or marker detection. The system consists of a 3x3 read-out CMOS image sensor, an analog Sobel stage and additional circuitry like operational amplifiers and comparators to compute a 1bit image with the edges present in the taken photo. This information can then be further processed digitally to detect specific shapes in order to control robot routines, for example. The architecture of the proposed system is highly desirable as dedicated analog hardware has significant advantages in terms of power and speed compared to digital implementations. The overall system is simulated with the help of a 3x3 CMOS image sensor IC as well as Cadence Virtuoso for analog circuit simulation and MATLAB to convert the sequential information back to an image, and compared to other state of the art CMOS image sensors with edge detection capability. The analog Sobel circuit runs with a clock of 10MHz and consumes less than 0.79mW average power for the computation of the example image, and the whole 200x200 pixel image sensor consumes only 5.5mW at a frame rate of 75 fps.},
    author = {Söll, Christopher and Shi, Lan and Röber, Jürgen and Reichenbach, Marc and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {IEEE International Conference on Image Processing (ICIP)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123903164},
    year = {2016},
    month = {09},
    doi = {10.1109/ICIP.2016.7533193},
    faupublication = {yes},
    keywords = {Smart Camera; CMOS Image Sensor; Analog Processing Circuits; Analog Sobel; GRK-1773},
    peerreviewed = {Yes},
    title = {Low-Power Analog Smart Camera Sensor for Edge Detection},
    venue = {Phoenix, USA},
    }
  • C. Söll, T. Mai, L. Shi, J. Röber, T. Ußmüller, R. Weigel, and A. Hagelauer, "Low-Power High-Gain Operational Amplifier for Analog Image Pre-Processing in Smart Sensor Systems" in 15. ITG/GMM-Fachtagung Analog 2016, Bremen, 2016, pp. 28-32. [Bibtex]
    @inproceedings{soell2016c,
    abstract = {In this work, a low-power high-gain operational amplifier is presented, which is dedicated to work in an analog image pre-processing stage in a smart sensor system. This stage is able to detect edges and shapes for instance, before the image is passed to the ADC and the digital computation stage, reducing data and precision requirement of both stages. This approach helps to save power, making smart image sensor nodes with energy harvesting reasonable. Since the precision as well as the energy consumption of the edge detection algorithm is highly depended on the amplifier used for the basic summing and multiplier blocks, the design of it plays an important role for the approach. The proposed input/output rail-to-rail operational amplifier is based on a 150 nm CMOS process, has a gain of 77 dB and a unity gain bandwidth of 45.7MHz while consuming only 77 µA statically at a supply voltage of 1.8V.},
    author = {Söll, Christopher and Mai, Timo and Shi, Lan and Röber, Jürgen and Ußmüller, Thomas and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {15. ITG/GMM-Fachtagung Analog 2016},
    cris = {https://cris.fau.de/converis/publicweb/publication/122848044},
    year = {2016},
    month = {09},
    faupublication = {yes},
    isbn = {9783800742653},
    keywords = {analog pre-processing; operational amplifier; low-power; high-gain; folded-cascode; GRK-1773},
    pages = {28--32},
    peerreviewed = {Yes},
    title = {Low-Power High-Gain Operational Amplifier for Analog Image Pre-Processing in Smart Sensor Systems},
    venue = {Bremen},
    }
  • J. Röber, S. Senega, A. Bänisch, A. Hagelauer, R. Weigel, and S. Lindenmeier, "Integrated Diversity Front-End for Digital Satellite Radio Reception" in IEEE MTT International Microwave Symposium (IMS), San Francisco, USA, 2016, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{roeber2016,
    abstract = {This paper presents a diversity integrated circuit (IC) for digital satellite radio (SDARS) at 2.3GHz. The IC contains an RF circuit which enables fast adaptive processing of up to three antenna signals for maximum ratio combining in a fast fading scenario. The RF front-end of the diversity system is integrated using 150 nm CMOS technology. The phase of each of the three input paths can be adjusted in quantized steps of 45° from 0° to 360°. If the input signal of one path suffers from fading, a single path can be completely turned off for reducing the power consumption. The diversity IC is evaluated by means of laboratory measurements as well as by tests where antenna signals of real fading scenarios are processed using the presented IC. The results showa typical improvement in radio reception of more than a factor of 4 compared to a conventional reception system.},
    author = {Röber, Jürgen and Senega, Simon and Bänisch, Andreas and Hagelauer, Amelie and Weigel, Robert and Lindenmeier, Stefan},
    publisher = {IEEE},
    booktitle = {IEEE MTT International Microwave Symposium (IMS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122840124},
    year = {2016},
    month = {05},
    doi = {10.1109/MWSYM.2016.7540318},
    eventtitle = {IEEE MTT International Microwave Symposium (IMS)},
    faupublication = {yes},
    keywords = {SDARS; Diversity; LNA; Phase Shifter; Power Combiner; Integrated Circuit; RF Front-end},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Integrated Diversity Front-End for Digital Satellite Radio Reception},
    venue = {San Francisco, USA},
    }
  • C. Hsieh, J. Röber, A. Bänisch, A. Hagelauer, T. Ußmüller, and R. Weigel, "A low power CMOS transmitter with Class-E power amplifiers for positioning application in multi-band" in GeMiC 2016, German Microwave Conference 2016, Bochum, Germany, 2016, pp. 433-436. [DOI] [Bibtex]
    @inproceedings{hsieh2016,
    abstract = {In this paper, a transmitter for outdoor positioning application such as animal tracking is introduced. Class-E power amplifiers are exploited in the transmitter system in order to increase the energy efficiency for the demand of long operation duration of the system. Along with the need of power saving, a circuit topology is proposed to realize the modulation based on Binary Offset Carrier (BOC) technique at two different bands to achieve higher positioning accuracy and better utilization of the spectrum by transmitting data simultaneously. The operating frequencies of the system are 868 MHz and 2.4 GHz, and the circuit is designed in 150nm CMOS technology. The power efficiency of the class-E power amplifier is greater than 50 % over 2.4-2.8 GHz while the measured output power is greater than 10 dBm from 1.3 to 2.8 GHz.},
    author = {Hsieh, Chia-Yu and Röber, Jürgen and Bänisch, Andreas and Hagelauer, Amelie and Ußmüller, Thomas and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {GeMiC 2016, German Microwave Conference 2016},
    cris = {https://cris.fau.de/converis/publicweb/publication/108093084},
    year = {2016},
    month = {03},
    doi = {10.1109/GEMIC.2016.7461648},
    eventtitle = {GeMiC 2016, German Microwave Conference 2016},
    faupublication = {yes},
    keywords = {positioning; class-E},
    pages = {433--436},
    peerreviewed = {Yes},
    title = {A low power CMOS transmitter with Class-E power amplifiers for positioning application in multi-band},
    venue = {Bochum, Germany},
    }
  • L. Classen, A. Kappes, T. Karg, A. Kretzschmann, A. Koelpin, S. Lindner, and J. Röber, "The mDOM - A multi-PMT optical module for IceCube-Gen2" in DPG-Verhandlungen, Hamburg, 2016. [Bibtex]
    @inproceedings{classen2016,
    abstract = {Following the discovery of an astrophysical neutrino flux by IceCube in 2013, planning is under way for the next generation neutrino telescope at the South Pole, IceCube-Gen2, which will significantly enhance and expand IceCube’s sensitivity both towards high neutrino energies as well as in the low-energy regime. In the scope of these efforts, a novel multi-PMT optical sensor is being developed which, following the KM3NeT design, consists of an array of several small PMTs inside a transparent pressure vessel. This design provides some significant advantages compared to the conventional single-PMT module design, such as an increased effective area, homogeneous coverage of the full solid angle, and intrinsic angular sensitivity. The talk presents an overview of the project and its current status, featuring hardware development, testing, and simulation efforts.},
    author = {Classen, Lew and Kappes, Alexander and Karg, Timo and Kretzschmann, Axel and Koelpin, Alexander and Lindner, Stefan and Röber, Jürgen},
    booktitle = {DPG-Verhandlungen},
    cris = {https://cris.fau.de/converis/publicweb/publication/106319884},
    year = {2016},
    month = {02},
    day = {29},
    eventdate = {2016-02-29/2016-03-04},
    eventtitle = {DPG-Verhandlungen},
    faupublication = {yes},
    issn = {0420-0195},
    peerreviewed = {unknown},
    title = {The mDOM - A multi-PMT optical module for IceCube-Gen2},
    url = {https://inis.iaea.org/search/search.aspx?orig_q=RN:48030386},
    venue = {Hamburg},
    }
  • R. Löhr, F. Ohnhäuser, J. Röber, and R. Weigel, "Switch Bootstrapping in a 1.5 Bit Pipeline Stage" in Analog2016, Bremen, 2016, pp. 49-52. [Bibtex]
    @inproceedings{loehr2016,
    abstract = {The targeted 16 bit pipeline converter has an adjustable sampling frequency from 100MHz to 200MHz. In this paper the switches for the input and the reference voltage sampling are analyzed. Therefore, a novel switch bootstrapping technique is presented, which guarantees a worst case input voltage settling accuracy of LSB 2 at settling times between 2 ns to 5 ns. The non-linearity caused by the input switches is simulated and typically amounts to -115 dB. In addition a possible solution for external reference voltage settling is introduced.},
    author = {Löhr, Robert and Ohnhäuser, Frank and Röber, Jürgen and Weigel, Robert},
    booktitle = {Analog2016},
    cris = {https://cris.fau.de/converis/publicweb/publication/122835064},
    year = {2016},
    eventtitle = {Analog2016},
    faupublication = {yes},
    keywords = {1.5 bit,switch bootstrapping,MDAC,charge injection,external reference,non-linearity},
    pages = {49--52},
    peerreviewed = {Yes},
    title = {Switch Bootstrapping in a 1.5 Bit Pipeline Stage},
    venue = {Bremen},
    }

2015

  • R. Löhr, M. Kempf, F. Ohnhäuser, J. Röber, R. Weigel, and A. Bänisch, "Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process" in International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Nusa Dua, Bali, 2015. [DOI] [Bibtex]
    @inproceedings{loehr2015,
    abstract = {Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.},
    author = {Löhr, Robert and Kempf, Markus and Ohnhäuser, Frank and Röber, Jürgen and Weigel, Robert and Bänisch, Andreas},
    booktitle = {International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/120749684},
    year = {2015},
    month = {11},
    doi = {10.1109/ISPACS.2015.7432788},
    eventtitle = {International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process},
    venue = {Nusa Dua, Bali},
    }
  • C. Lindner, C. Söll, J. Röber, A. Bänisch, and R. Weigel, "Yield Analysation and Optimization Methods for Active CMOS Pixels" in 8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Siegen, Germany, 2015, pp. 107-114. [Bibtex]
    @inproceedings{lindner2015b,
    abstract = {This work explains how to simulate error sources in image sensors to analyze yield. Moreover, two circuitry-wise methods to reduce these interferences are proposed and their influences on yield and standard deviation caused by process variations and reset noise are analyzed. Thereby the biggest sources of interference within the pixel architectures are described. After comparing three different pixel architectures, their extracted layout is simulated and the results are compared. Especially the change of the yield and the standard deviation with and without the use of DS and CDS are analyzed. By applying the methods mentioned before the yield could be increased by up to 15.6 %.},
    author = {Lindner, Claus and Söll, Christopher and Röber, Jürgen and Bänisch, Andreas and Weigel, Robert},
    booktitle = {8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122818124},
    year = {2015},
    month = {09},
    faupublication = {yes},
    isbn = {9783800740710},
    keywords = {Yield Analysis; Active Cmos Pixel; Image Sensor; Correlated Double Sampling; Double Sampling; Simulation Method; GRK-1773},
    pages = {107--114},
    peerreviewed = {Yes},
    title = {Yield Analysation and Optimization Methods for Active CMOS Pixels},
    venue = {Siegen, Germany},
    }
  • J. Röber, C. Zwick, A. Bänisch, S. Dirauf, G. Roppenecker, R. Weigel, and S. Dirauf, "Novel Control Methods for Phase Lock Loops" in European conference on circuit theory and design (ECCTD), Trondheim, 2015. [DOI] [Bibtex]
    @inproceedings{roeber2015a,
    abstract = {This paper discusses different approaches to improve the settling behavior of phase lock loops (PLL). Starting with a state-of-the-art PLL, a structure with an additional dynamic changing Loop-Filter and another structure with feed forward control are proposed. The main point of this paper is the adaption of modern control theory in the design of PLL systems to improve the behavior in case of a changing dividing factor and thereby the output frequency. For both structures, advantages and disadvantages are discussed and then the block diagram of the two approaches are presented. Both methods are compared to the state-of-the-art by simulations in MatLab Simulink. Therefore a massive changing output frequency of the PLL and the corresponding time for locking to the new output frequency is analyzed. All in all both novel PLL concepts offer a reduced settling time with respect to a specified change of the PLL output frequency.},
    author = {Röber, Jürgen and Zwick, Christian and Bänisch, Andreas and Dirauf, Simon and Roppenecker, Günter and Weigel, Robert and Dirauf, Simon},
    publisher = {IEEE},
    booktitle = {European conference on circuit theory and design (ECCTD)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123893924},
    year = {2015},
    month = {08},
    doi = {10.1109/ECCTD.2015.7300091},
    eventtitle = {European conference on circuit theory and design (ECCTD)},
    faupublication = {yes},
    keywords = {PLL; Phase Lock Loop; Synthesizer; Control Theory; Behavioral Modeling},
    peerreviewed = {Yes},
    title = {Novel Control Methods for Phase Lock Loops},
    venue = {Trondheim},
    }
  • C. Söll, L. Shi, A. Bänisch, J. Röber, T. Ußmüller, and R. Weigel, "Analog Computation Methods with the help of analog and pseudo-digital Carry Signals" in IEEE European conference on circuit theory and design (ECCTD), Trondheim, 2015, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{soell2015a,
    abstract = {This work describes new methods of handling exceedings of the supply range in analog computation stages. These are handled as pseudo-digital and analog carry signals and used to regulate the gain of the stage where they occur as well as all computation stages that follow. A complete example for such an analog computation is simulated and presented and critical parts of the architectures are addressed. In addition, more sophisticated extensions are proposed and the ”right” way of carry handling is explained for a specific algorithm, together with a discussion of the advantages of different methods for each application.},
    author = {Söll, Christopher and Shi, Lan and Bänisch, Andreas and Röber, Jürgen and Ußmüller, Thomas and Weigel, Robert},
    booktitle = {IEEE European conference on circuit theory and design (ECCTD)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108075484},
    year = {2015},
    month = {08},
    doi = {10.1109/ECCTD.2015.7300039},
    faupublication = {yes},
    keywords = {analog computation; analog carry; pseudo-digital carry; pre-processing; GRK-1773},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Analog Computation Methods with the help of analog and pseudo-digital Carry Signals},
    venue = {Trondheim},
    }
  • C. Söll, A. Bänisch, J. Röber, L. Shi, and R. Weigel, "A Multi-Functional Reconfigurable Low-Power Ultra-High PSRR CMOS Reference-System" in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, 2015, pp. 220-223. [DOI] [Bibtex]
    @inproceedings{soell2015,
    abstract = {This paper presents a new reference system with emphasis on low power design and high power supply rejection. The untrimmed reference provides a 600mV output voltage, which only differs by 5.75mV in the temperature range between -40 ° C and +125 ° C and a PSRR of -157.2 dB at 10Hz. The core part of the reference produces a reference potential of 416.1mV with a deviation of only 1.59mV. Moreover, the circuit provides a 900mV output, a temperature independent 3 µA current and trimming possibilities for the temperature curves and the amplitude of output voltages and currents. Under all operating conditions, the post-layout Corner- and Monte-Carlo-Simulations show a power consumption of less than 40 µA and ensure functionality across process, supply voltage and temperature variations.},
    author = {Söll, Christopher and Bänisch, Andreas and Röber, Jürgen and Shi, Lan and Weigel, Robert},
    booktitle = {IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108045124},
    year = {2015},
    month = {06},
    doi = {10.1109/PRIME.2015.7251374},
    faupublication = {yes},
    keywords = {bandgap; reference; low power; high psrr; temperature coefficient; subregulation; GRK-1773},
    pages = {220--223},
    peerreviewed = {Yes},
    title = {A Multi-Functional Reconfigurable Low-Power Ultra-High PSRR CMOS Reference-System},
    venue = {Glasgow},
    }
  • J. Röber, A. Bänisch, G. Fischer, and R. Weigel, "A Low Noise Amplifier Chain for Digital Satellite Radio Applications" in IEEE International Symposium on Circuits and Systems (ISCAS), Lisabon, 2015. [DOI] [Bibtex]
    @inproceedings{roeber2015,
    abstract = {This paper contains the development and verification of low noise amplifier stages (LNA) within the framework of a front-end for digital satellite radio diversity receiver operating around 2.3 GHz. First, a low noise high gain LNA is developed to reach the high requirements of satellite radio reception. Therefore a single-ended cascode architecture is chosen. The simulated noise figure is 0.58 dB and the gain is 19.87 dB. Second, a differential stage is designed to fulfill the specification with regards to backward isolation and common-mode rejection. This circuit has a measured gain of 10.15 dB and a backward isolation of -43.24 dB. Furthermore, the two stages are combined by an integrated balun and the overall performance is verified. Due to the good noise performance of the first stage, the overall noise figure is 0.64 dB, the gain is 29.83 dB and the backward isolation is - 76.07 dB. All in all the whole circuit has a current consumption of 25.40 mA. Finally the LNA performance is compared with other state-of-the-art LNAs.},
    author = {Röber, Jürgen and Bänisch, Andreas and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108061184},
    year = {2015},
    month = {05},
    doi = {10.1109/ISCAS.2015.7169187},
    eventtitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
    faupublication = {yes},
    keywords = {LNA; low noise; high gain; differential; distortion canceller; CCPDC},
    peerreviewed = {Yes},
    title = {A Low Noise Amplifier Chain for Digital Satellite Radio Applications},
    venue = {Lisabon},
    }
  • T. Kastenhuber, J. Röber, A. Bänisch, G. Fischer, and R. Weigel, "A Miniaturized Very Low-Power Vector Modulated CMOS Phase Shifter for Wireless Receivers" in German Microwave Conference, Nürnberg, 2015, pp. 343-346. [DOI] [Bibtex]
    @inproceedings{kastenhuber2015,
    abstract = {This paper presents and analyses a phase shifter for diversity receivers, which modulates the I-/Q-vector in the constellation diagram. The system consists of a three stage programmable gain amplifier (PGA) chain in both branches. The design covers the full phase range of 360°. Each stage can be programmed to amplify the incoming signal between 19 dB and 63 dB with a centre frequency of 3MHz. The radio frequency (RF) signal is down-converted to an intermediate frequency (IF) of 5MHz, where phase shifting is done. The circuit is intended for an automotive satellite radio receiver in S- and L-band. Thus, demand automotive requirements have to be fulfilled. The supply voltage is 1.8V. Compared to other phase shifters, the power consumption of 2.7mW is highly energyefficient. This system includes a constant gm-source and a biasing circuit. All requirements are verified in post-layout Corner and Monte−Carlo analysis using Virtuoso and WiCkeD. The design only takes 0.116 mm2 of silicon area in a 150- nm CMOS technology.},
    author = {Kastenhuber, Tina and Röber, Jürgen and Bänisch, Andreas and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {German Microwave Conference},
    cris = {https://cris.fau.de/converis/publicweb/publication/108077464},
    year = {2015},
    month = {03},
    doi = {10.1109/GEMIC.2015.7107823},
    eventtitle = {German Microwave Conference},
    faupublication = {yes},
    keywords = {Phase shifter; vector modulated; PGA; constant gm-source; low-power; diversity},
    pages = {343--346},
    peerreviewed = {Yes},
    title = {A Miniaturized Very Low-Power Vector Modulated CMOS Phase Shifter for Wireless Receivers},
    venue = {Nürnberg},
    }

2014

  • J. Röber, A. Bänisch, T. Ußmüller, G. Fischer, and R. Weigel, "Frequency Synthesizer for Digital Satellite Radio Receiving Systems" in IEEE International Wireless Symposium (IWS) 2014, Xi'an China, 2014, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{roeber2014,
    abstract = {This paper describes the design and verification of phase lock loop (PLL) components within the framework of a front-end for digital satellite radio diversity reception. First, the functionality of the implemented PLL is described by a block diagram. Second, individual PLL components are presented and analysed. Altogether a voltage controlled oscillator (VCO), an automatic amplitude control (AAC), a buffer stage, a TSCP logic as well as a DCVSL-R high-speed by-two-divider, a multimodulus divider (MMD), and a phase-frequency detector are developed. The frequency tuning range of the PLL is between 4.34 and 4.70 GHz and hence the VCO tuning range has to be around 4 to 5 GHz. Beyond this, the VCO’s post-layout phase noise is -100.50 dBc/Hz at 1 MHz under nominal environmental conditions and the post-layout yield analysis predicts 99.773%. Additionally, the VCO and the AAC are connected. Due to that additional AAC feedback circuit, the current consumption as well as the VCO output amplitude decrease. The overall system simulation shows the settling process of the PLL for the tri-state and the five-state mode of the PFD. Finally the VCO performance is compared with other state-of-the-art LC-VCOs.},
    author = {Röber, Jürgen and Bänisch, Andreas and Ußmüller, Thomas and Fischer, Georg and Weigel, Robert},
    language = {English},
    publisher = {IEEE},
    booktitle = {IEEE International Wireless Symposium (IWS) 2014},
    cris = {https://cris.fau.de/converis/publicweb/publication/120707224},
    year = {2014},
    month = {03},
    day = {24},
    doi = {10.1109/IEEE-IWS.2014.6864267},
    eventdate = {2014-03-24/2014-03-26},
    eventtitle = {2014 IEEE International Wireless Symposium (IWS 2014)},
    faupublication = {yes},
    keywords = {PLL; Synthesizer; Mixed-Signal; VCO; AAC; Behavioral Modeling; Diversity},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Frequency Synthesizer for Digital Satellite Radio Receiving Systems},
    type = {Konferenzschrift},
    url = {http://ieeexplore.ieee.org/document/6864267/},
    venue = {Xi'an China},
    }

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