Staff

Prof. Dr. Jan-Erik Müller

Lectures Summer term 2019

Lectures Winter term 2019

Warnung: Bibtex-Parsing nicht konfiguriert im Profil, verwende Standard-Werte

Patents

  • A. Zohny, S. Leuschner, and J. Müller, Amplifier and Mobile Communication Device, 2012. [Bibtex]
    @patent{zohny_patent_2012,
    abstract = {The goal of this invention is then to utilize a novel linearization scheme in order to decrease the amount of back-off needed from the PA. Thus, the efficiency for a certain linearity requirement can be boosted and a longer battery-life is achieved.},
    author = {Zohny, Amr and Leuschner, Stephan and Müller, Jan-Erik},
    cris = {zohny_patent_2012},
    year = {2012},
    month = {05},
    day = {16},
    keywords = {Power Amplifier,Distortion,PAE,Linearity,WCDMA,CMOS},
    number = {US9088248},
    title = {Amplifier and Mobile Communication Device},
    type = {patent},
    url = {http://ip.com/pat/US9088248},
    }

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Publications

2015

  • S. Glock, J. Rascher, B. Sogl, T. Ußmüller, J. Müller, and R. Weigel, "A Memoryless Semi-Physical Power Amplifier Behavioral Model Based on the Correlation Between AM-AM and AM-PM Distortions", IEEE Transactions on Microwave Theory and Techniques, vol. 63, iss. 6, pp. 1826-1835, 2015. [DOI] [Bibtex]
    @article{glock2015,
    abstract = {A new semi-physical memoryless computationally effective behavioral model (BM) capable of predicting amplitude-modulation-to-amplitude-modulation (AM-AM) and amplitude-modulation-to-phase-modulation (AM-PM) distortions is proposed. In recent years, AM-AM and AM-PM distortions have been separately studied in literature. Here, we investigate the correlation between AM-AM and AM-PM distortions first. Based on the observed correlation, a novel AM-PM model is derived from the well-known Rapp AM-AM model. On the basis of the close relationship between the AM-AM and AM-PM model, a highly accurate and computationally effective large-signal BM is obtained. The newly developed model addresses the current needs of the mobile industry that requires BMs of the power amplifier (PA), which can be interpreted by the designers. In addition, the models must be computationally effective due to the limited computation power in mobile handset. Therefore, only memoryless BMs can be taken into account and larger errors are accepted for the sake of computational effectiveness. In this paper, it is shown that the newly introduced model achieves excellent results, when it is applied to actual industrial applications of two GaAs-based class-AB PAs in 65-nm technology and one CMOS-based class AB PA in 28-nm technology, which are designed for mobile communications.},
    author = {Glock, Stefan and Rascher, Jochen and Sogl, Bernhard and Ußmüller, Thomas and Müller, Jan-Erik and Weigel, Robert},
    cris = {https://cris.fau.de/converis/publicweb/publication/120736264},
    year = {2015},
    month = {06},
    doi = {10.1109/TMTT.2015.2418751},
    faupublication = {yes},
    issn = {0018-9480},
    journaltitle = {IEEE Transactions on Microwave Theory and Techniques},
    number = {6},
    pages = {1826--1835},
    peerreviewed = {Yes},
    shortjournal = {IEEE T MICROW THEORY},
    title = {A Memoryless Semi-Physical Power Amplifier Behavioral Model Based on the Correlation Between AM-AM and AM-PM Distortions},
    volume = {63},
    }
  • A. Cattaneo, S. Pinarello, J. Müller, and R. Weigel, "Impact of DC and RF non-conducting stress on nMOS reliability" in IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2015, p. XT4.1--XT4.4. [DOI] [Bibtex]
    @inproceedings{cattaneo2015,
    abstract = {The increase of leakage current in deep-submicrometer MOS transistors operated below threshold is becoming a reliability concern for scaled technology nodes. Especially high-power analog applications like high efficiency PAs and RF-switches undergo to strong lateral field when Vg <;Vth. Indeed an increased degradation for these MOS applications was already reported in the state of the art but not completely understood. In this paper a thorough study of the DC non-conducting (NC) stress is presented and a new physical model describing the worsening of the electrical parameter is proposed. This model is suitable for being extended to the high frequency regime by means of a quasi-static sum (QS). For the first time RF stress measurements are conducted in various NC configurations. No frequency dependency is detected up to 4Ghz and the QS model is able to precisely predict the performance degradation.},
    author = {Cattaneo, Andrea and Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {IEEE International Reliability Physics Symposium (IRPS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122826704},
    year = {2015},
    month = {04},
    day = {19},
    doi = {10.1109/IRPS.2015.7112835},
    eventdate = {2015-04-19/2015-04-23},
    faupublication = {yes},
    pages = {XT4.1--XT4.4},
    peerreviewed = {unknown},
    title = {Impact of DC and RF non-conducting stress on nMOS reliability},
    venue = {Monterey, CA, USA},
    }

2014

  • A. Farabegoli, B. Sogl, J. Müller, and R. Weigel, "A Novel Crest Factor Reduction Technique using Memoryless Polynomials" in 44th European Microwave Conference (EuMC), Rom, Italy, 2014, pp. 825-828. [DOI] [Bibtex]
    @inproceedings{farabegoli2014,
    author = {Farabegoli, Alessio and Sogl, Bernhard and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {44th European Microwave Conference (EuMC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123877644},
    year = {2014},
    month = {10},
    day = {06},
    doi = {10.1109/EUMC.2014.6986562},
    eventdate = {2014-10-06/2014-10-09},
    faupublication = {yes},
    pages = {825--828},
    peerreviewed = {Yes},
    title = {A Novel Crest Factor Reduction Technique using Memoryless Polynomials},
    venue = {Rom, Italy},
    }
  • A. Cattaneo, S. Pinarello, J. Müller, and R. Weigel, "Frequency Response of Stress-Effects on CMOS Power Amplifiers" in IEEE International Integrated Reliability Workshop Final Report (IIRW), South Lake Tahoe, USA, 2014, pp. 79-81. [DOI] [Bibtex]
    @inproceedings{cattaneo2014a,
    abstract = {RF Power Amplifiers (PAs) undergo to high electrical stress conditions due to strong lateral field along the channel. Reliability of CMOS PAs is largely studied in literature. Generally is focused in understanding how RF stress can harm the device. Many authors proved that the generation of defects does not have a frequency dependency. In this work the problem is faced from a new point of view. The response of the defects, instead of the generation, is studied over frequency. It is demonstrated that the electrons-trapping by interface states is quenched by increasing the operation frequency. As a consequence the performance of the PA are recovered. This finding points out for the first time the possibility of relaxing the reliability constrains when operating in RF regime.},
    author = {Cattaneo, Andrea and Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {IEEE International Integrated Reliability Workshop Final Report (IIRW)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122785564},
    year = {2014},
    month = {10},
    day = {12},
    doi = {10.1109/IIRW.2014.7049515},
    eventdate = {2014-10-12/2014-10-16},
    faupublication = {yes},
    pages = {79--81},
    peerreviewed = {Yes},
    title = {Frequency Response of Stress-Effects on CMOS Power Amplifiers},
    venue = {South Lake Tahoe, USA},
    }
  • A. Cattaneo, S. Pinarello, J. Müller, and R. Weigel, "MOSFET degradation under DC and RF Fowler-Nordheim stress" in 44th European Solid State Device Research Conference (ESSDERC), Venice, Italy, 2014, pp. 230-233. [DOI] [Bibtex]
    @inproceedings{cattaneo2014,
    abstract = {Fowler-Nordheim (F-N) stress is reported to be one of the most severe wear-out mechanisms for high-frequency MOSFET applications like PAs and RF switches. Previous studies of this degradation process were limited to the DC-static case only and standard empirical models were proposed. In this work a novel general physical model is developed, which correctly describes the ageing of electrical parameters under DC stress. This is made possible by taking into account the hole injection into the gate oxide. Finally this study extends the understanding of F-N degradation to RF regime. In this case a quasi-static sum of the degradation rate is adopted to accurately model and predict the performance worsening; the wear-out shows no frequency dependency in the range up to 4Ghz.},
    author = {Cattaneo, Andrea and Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {44th European Solid State Device Research Conference (ESSDERC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/106951944},
    year = {2014},
    month = {09},
    day = {22},
    doi = {10.1109/ESSDERC.2014.6948802},
    eventdate = {2014-09-22/2014-09-26},
    faupublication = {yes},
    pages = {230--233},
    peerreviewed = {Yes},
    title = {MOSFET degradation under DC and RF Fowler-Nordheim stress},
    venue = {Venice, Italy},
    }
  • A. Farabegoli, B. Sogl, J. Müller, and R. Weigel, "Advanced transmitters with combined crest factor reduction and digital predistortion techniques" in Radio and Wireless Symposium (RWS), 2014 IEEE, 2014. [DOI] [Bibtex]
    @inproceedings{farabegoli2014a,
    author = {Farabegoli, Alessio and Sogl, Bernhard and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {Radio and Wireless Symposium (RWS), 2014 IEEE},
    cris = {https://cris.fau.de/converis/publicweb/publication/122905244},
    year = {2014},
    month = {06},
    day = {19},
    doi = {10.1109/RWS.2014.6830153},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Advanced transmitters with combined crest factor reduction and digital predistortion techniques},
    type = {Konferenzschrift},
    }
  • S. Glock, J. Rascher, B. Sogl, T. Ußmüller, J. Müller, G. Fischer, and R. Weigel, "A Semi-Physical Power Amplifier Behavioral Model Capable of Predicting Gain Expansion Effects" in IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications, Newport Beach, CA, USA, 2014, pp. 1-3. [DOI] [Bibtex]
    @inproceedings{glock2014,
    abstract = {A novel semi-physical power amplifier (PA) behavioral model (BM) that describes the input-output characteristic of PAs exhibiting gain expansion (GE) is introduced. The accurate prediction of GE is of particular importance because GE typically improves the power added efficiency (PAE) at high input powers. Though, GE impacts the spectral regrowth. Therefore, BMs that are capable of predicting GE, like the one introduced in this work, are highly desirable. In a case study, the proposed model is employed to predict the AM-AM distortions of a GaAs PA designed for LTE applications. Excellent agreement between measurement and simulation results is obtained. The computational efficient model allows system-level simulations of advanced transmitter systems in order to optimize their modes of operation.},
    author = {Glock, Stefan and Rascher, Jochen and Sogl, Bernhard and Ußmüller, Thomas and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications},
    cris = {https://cris.fau.de/converis/publicweb/publication/122756744},
    year = {2014},
    month = {01},
    day = {19},
    doi = {10.1109/PAWR.2014.6825726},
    eventdate = {2014-01-19/2014-01-23},
    faupublication = {yes},
    pages = {1--3},
    peerreviewed = {Yes},
    title = {A Semi-Physical Power Amplifier Behavioral Model Capable of Predicting Gain Expansion Effects},
    venue = {Newport Beach, CA, USA},
    }

2013

  • S. Glock, J. Rascher, B. Sogl, T. Ußmüller, J. Müller, G. Fischer, and R. Weigel, "A Novel Power Amplifier Behavioral Model for Improving the Linearity-Efficiency Tradeoff" in International Microwave and RF Conference (IMaRC), New Delhi, India, 2013, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{glock2013c,
    abstract = {This paper focuses on a novel power amplifier (PA) semi-physical behavioral model (BM) to study the linearityefficiency trade-off in modern wireless transmitter systems. While the behavioral models known in the literature mainly focus on the precise description of the PA nonlinearity in terms of amplitudemodulation- to-amplitude-modulation (AM-AM) and amplitudemodulation- to-phase-modulation (AM-PM) distortions, the model introduced here, also predicts the DC current flowing from the power supply to the PA. This allows to optimize the battery current while keeping the out-of-channel interference within specification limits. In a case study, the DC current and the amplitude distortions of a PA, designed for IEEE 802.11b/g/n applications are predicted with a normalized mean square error (NMSE) of -39.92 dB and -47.07 dB, respectively.},
    author = {Glock, Stefan and Rascher, Jochen and Sogl, Bernhard and Ußmüller, Thomas and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {International Microwave and RF Conference (IMaRC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122705044},
    year = {2013},
    month = {12},
    doi = {10.1109/IMARC.2013.6777718},
    faupublication = {yes},
    pages = {1--4},
    peerreviewed = {unknown},
    title = {A Novel Power Amplifier Behavioral Model for Improving the Linearity-Efficiency Tradeoff},
    venue = {New Delhi, India},
    }
  • S. Pinarello, J. Müller, and R. Weigel, "Extension of the Load-Line Theory by Investigating the Impact of the Knee-Voltage on Output-Power and Efficiency" in European Microwave Integrated Circuits Conference, Nuremberg, Germany, 2013, pp. 488-491. [Bibtex]
    @inproceedings{sandro2013,
    abstract = {The standard load-line theory for power amplifier (PA) design becomes inaccurate when the ratio of the transistor's knee-voltage to the supply voltage gets larger than one. This is often the case for sub-micron CMOS PA designs due to low breakdown voltage. Based on simple geometrical reasoning the load-line theory is generalized to include these cases. The optimum load impedance that results in maximum output power, the maximum power achieved, and the corresponding efficiency are derived in closed form. The efficiency can be improved by backing off the output power. The trade-off between output power and simultaneously achievable efficiency as a function of the knee-voltage is discussed.},
    author = {Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {European Microwave Integrated Circuits Conference},
    cris = {https://cris.fau.de/converis/publicweb/publication/106925544},
    year = {2013},
    month = {10},
    day = {06},
    eventdate = {2013-10-06/2013-10-10},
    faupublication = {yes},
    pages = {488--491},
    peerreviewed = {Yes},
    title = {Extension of the Load-Line Theory by Investigating the Impact of the Knee-Voltage on Output-Power and Efficiency},
    venue = {Nuremberg, Germany},
    }
  • S. Pinarello, J. Müller, and R. Weigel, "Comparative Evaluation of Different Current Saving Strategies for Power Amplifiers in Back-Off Operation" in European Microwave Conference (EuMC), Nuremberg, DE, 2013, pp. 557-560. [Bibtex]
    @inproceedings{weigel2013a,
    abstract = {Three different methodologies are compared, which are suitable for saving battery current of a power amplifier operated in back-off. Dynamic Voltage Biasing (DVB), Dynamic Current Biasing (DCB), and Load Modulation (LM) have been paired in three different ways and experimentally tested for the first time on the same power transistor to achieve meaningful conclusions. Measurement results from on-wafer load-pull investigation of a SiGe power cell identify the combination of DVB and DCB as the most profitable strategy. This mode manifests a power added efficiency higher than 75% for an excellent 14dB back-off dynamic.},
    author = {Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {European Microwave Conference (EuMC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123385064},
    year = {2013},
    month = {10},
    day = {06},
    eventdate = {2013-10-06/2013-10-10},
    faupublication = {yes},
    keywords = {modulation; power amplifiers; power transistors; DCB; DVB; LM; back-off operation; battery current; current saving strategies; dynamic current biasing; Digital video broadcasting; Frequency measurement},
    pages = {557--560},
    peerreviewed = {Yes},
    title = {Comparative Evaluation of Different Current Saving Strategies for Power Amplifiers in Back-Off Operation},
    url = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6686716},
    venue = {Nuremberg, DE},
    }
  • A. Zohny, S. Leuschner, J. Rascher, S. Pinarello, T. Ußmüller, J. Müller, G. Fischer, and R. Weigel, "Analog Compensation of AM-AM and AM-PM effects for HighEfficiency Stacked-FET Power Amplifiers in 65-nm Standard CMOS" in European Microwave Integrated Circuits Conference (EuMIC), Nürnberg, 2013, pp. 165-168. [Bibtex]
    @inproceedings{zohny2013a,
    abstract = {Simultaneously achieving high linearity and high power-added efficiency (PAE) is essential for power amplifiers (PA) operating with modern communication signals. The challenge is exacerbated by the low breakdown voltages of standard CMOS realizations. This work presents a low-complexity programmable analog scheme to compensate the strong AM-AM and AM-PM nonlinearities of the high-ruggedness stacked-cascode topology while maintaining high PAE. The proposed solution utilizes standard NMOS devices to achieve peak PAE of 60% at the 900 MHz band from a 3V supply. The compensation scheme manages to improve the output 1-dB compression point by up to 2 dB and keep the AM-PM variation within 5 degrees. The proposed method improves the linear output power (@ ACPR= -40 dBc) for a Class-AB power amplifier by up to 1.5 dB without compromising PAE or saturated output power},
    author = {Zohny, Amr and Leuschner, Stephan and Rascher, Jochen and Pinarello, Sandro and Ußmüller, Thomas and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {European Microwave Integrated Circuits Conference (EuMIC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108006624},
    year = {2013},
    month = {10},
    day = {06},
    eventdate = {2013-10-06/2013-10-08},
    faupublication = {yes},
    keywords = {Power amplifier; Stacked FET; Stacked cascode; CMOS; linearization; ruggedness},
    pages = {165--168},
    peerreviewed = {Yes},
    title = {Analog Compensation of AM-AM and AM-PM effects for HighEfficiency Stacked-FET Power Amplifiers in 65-nm Standard CMOS},
    venue = {Nürnberg},
    }
  • A. Farabegoli, B. Sogl, J. Müller, and R. Weigel, "A novel, fast, and precise Method to perform Time Alignment Estimation and Compensation" in IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), Santa Clara, CA, 2013, pp. 28-30. [DOI] [Bibtex]
    @inproceedings{farabegoli2013,
    abstract = {In this paper, a novel procedure to estimate and compensate the delay between power amplifier's input and output waveforms is described. The proposed method has been developed in order to achieve fast computation and simple implementation that are required in state of the art mobile applications. In addition, the modular approach adopted offers high flexibility and enables further future improvements. Comparison with a traditional method like cross-correlation shows up to four times faster estimation time with the same precision. Resolution is furthermore improved estimating the fractional delay mismatch to increase the precision of the results with reduced sampling rate of the signals.},
    author = {Farabegoli, Alessio and Sogl, Bernhard and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122743544},
    year = {2013},
    month = {01},
    doi = {10.1109/PAWR.2013.6490178},
    faupublication = {yes},
    keywords = {power amplifiers; cross-correlation; fractional delay mismatch estimation; mobile application; modular approach; power amplifier; reduced sampling rate; time alignment compensation},
    pages = {28--30},
    peerreviewed = {Yes},
    title = {A novel, fast, and precise Method to perform Time Alignment Estimation and Compensation},
    venue = {Santa Clara, CA},
    }
  • S. Glock, B. Sogl, P. Vizaretta, T. Ußmüller, J. Müller, G. Fischer, and R. Weigel, "An Extension of Power Amplifier Behavioral Models for Optimizing Battery Current at System Level" in IEEE Radio and Wireless Week, Austin, TX, USA, 2013. [DOI] [Bibtex]
    @inproceedings{glock2013,
    abstract = {One of the most significant figures of merit concerning a power amplifier is its effficiency. However, behavioral models of power amplifiers are mainly focused on functional aspects but not on current consumption. Therefore, simulations with respect to the efficiency of a power amplifier cannot be accomplished at system level. To close the gap of simulation capabilities, this article proposes a time efficient and accurate extension of behavioral models to predict current consumption. The current consumption model accounts for different bias conditions. For a commercial handset power amplifier, an average error of 1.9% between the fast highlevel model and measurement results is obtained.},
    author = {Glock, Stefan and Sogl, Bernhard and Vizaretta, P. and Ußmüller, Thomas and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {IEEE Radio and Wireless Week},
    cris = {https://cris.fau.de/converis/publicweb/publication/120635064},
    year = {2013},
    month = {01},
    doi = {10.1109/PAWR.2013.6490191},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {An Extension of Power Amplifier Behavioral Models for Optimizing Battery Current at System Level},
    venue = {Austin, TX, USA},
    }

2012

  • A. Zohny, S. Leuschner, M. Kastner, J. Rascher, T. Ußmüller, J. Müller, G. Fischer, and R. Weigel, "Time-Efficient Adjacent Channel Power Ratio Simulation utilizing Overlap-add Signal Decomposition for UMTS Power Amplifiers" in Asia-Pacific Microwave Conference - APMC 2012, Kaohsiung, Taiwan, 2012. [DOI] [Bibtex]
    @inproceedings{zohny2012b,
    abstract = {The suitability of an RF power amplifier (PA) for modern sophisticated modulation schemes demands high linearity. One of the most significant figures of merit concerning PA linearity is its adjacent channel power ratio (ACPR). The aim of this paper is to propose a time-efficient simulation procedure for ACPR which conforms with the latest 3GPP TS 25.101 specifications for its calculation. This procedure overcomes the time penalty associated with the traditional envelope-based simulation method. The approach is based on standard harmonic balance (HB) tools with MATLAB post-processing incorporating the Overlap-add (OLA) signal decomposition DSP technique for fast RRC filtering. In addition, the simulation results are compared with measurements of a commercial WCDMA PA for verification. Accuracies of better than 0.5dB and 1.1dB are achieved up to 10dB and 2dB backoff respectively.},
    author = {Zohny, Amr and Leuschner, Stephan and Kastner, M. and Rascher, Jochen and Ußmüller, Thomas and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {Asia-Pacific Microwave Conference - APMC 2012},
    cris = {https://cris.fau.de/converis/publicweb/publication/107932484},
    year = {2012},
    month = {12},
    doi = {10.1109/APMC.2012.6421641},
    faupublication = {yes},
    keywords = {Power Amplifier; Linearity; ACPR; WCDMA; Distortion; Harmonic Balance},
    peerreviewed = {unknown},
    title = {Time-Efficient Adjacent Channel Power Ratio Simulation utilizing Overlap-add Signal Decomposition for UMTS Power Amplifiers},
    venue = {Kaohsiung, Taiwan},
    }
  • J. Rascher, S. Pinarello, J. Müller, G. Fischer, and R. Weigel, "Highly linear robust RF switch with low insertion loss and high power handling capability in a 65nm CMOS technology" in 2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Santa Clara, USA, 2012, pp. 21-24. [DOI] [Bibtex]
    @inproceedings{rascher2012,
    abstract = {This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of power handling and an input third order intermodulation intercept point (iIP3) of 48.8 dBm has been achieved at 1.8 GHz. High robustness is achieved by stacking 4 transistors. Isolation at 1.8 GHz is better than 22dB. For high power handling capability in off state a method is implemented to rise the DC voltage level at inner nodes of the switch. Thus the threshold voltage lowering in deeply scaled CMOS can be counteracted. The small and large signal behaviour of the switch is compared to conventional designs and benefits are proven.},
    author = {Rascher, Jochen and Pinarello, Sandro and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    booktitle = {2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)},
    cris = {https://cris.fau.de/converis/publicweb/publication/120573024},
    year = {2012},
    month = {01},
    doi = {10.1109/SIRF.2012.6160157},
    faupublication = {yes},
    isbn = {9781457713170},
    pages = {21--24},
    peerreviewed = {unknown},
    title = {Highly linear robust RF switch with low insertion loss and high power handling capability in a 65nm CMOS technology},
    venue = {Santa Clara, USA},
    }

2011

  • J. Rascher, S. Pinarello, J. Müller, G. Fischer, and R. Weigel, "Methods for Low Insertion Loss RF Switches with Increased Power Handling Capability in 65nm CMOS" in Asia-Pacific Microwave Conference 2011 (APMC 2011), Melbourne, Australia, 2011, pp. 1897-1900. [Bibtex]
    @inproceedings{rascher2011a,
    abstract = {This work reports on methods and dependencies for the design of low insertion loss single pole single throw (SPST) switches in 65nm CMOS with triple well transistors. Two different switch types are investigated and implemented. The series switch has less than 1dB insertion loss at 1.8GHz and a 1dB input compression point (P1dB) of 28.8dBm. The shunt switch has less than 0.4dB insertion loss at 1.8GHz and a P1dB of 29.1dBm. Isolation of the series and shunt switches at 1.8GHz is better than 21dB and 20dB, respectively. By applying a resistive body floating technique low insertion loss and increased power handling capability are achieved. At the shunt switch negative gate bias is adopted for improved P1dB. At the series switch a method is implemented to boost the DC voltage level at source/ drain nodes of transistors for improved power handling capability in off state without additional circuitry or any DC power consumption. The combination of these methods andan additional DC voltage in on state increases power handling capability in both states of the switch.},
    author = {Rascher, Jochen and Pinarello, Sandro and Müller, Jan-Erik and Fischer, Georg and Weigel, Robert},
    booktitle = {Asia-Pacific Microwave Conference 2011 (APMC 2011)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122399464},
    year = {2011},
    month = {12},
    faupublication = {yes},
    pages = {1897--1900},
    peerreviewed = {unknown},
    title = {Methods for Low Insertion Loss RF Switches with Increased Power Handling Capability in 65nm CMOS},
    venue = {Melbourne, Australia},
    }
  • V. Teppati, S. Pinarello, A. Ferrero, and J. Müller, "An unconventional VNA-based time-domain waveform load-pull test bench" in Microwave Conference Proceedings (APMC), 2010 Asia-Pacific, 2011. [Bibtex]
    @inproceedings{teppati2010,
    author = {Teppati, Valeria and Pinarello, Sandro and Ferrero, Andrea and Müller, Jan-Erik},
    booktitle = {Microwave Conference Proceedings (APMC), 2010 Asia-Pacific},
    cris = {https://cris.fau.de/converis/publicweb/publication/122236664},
    year = {2011},
    month = {12},
    day = {07},
    eventdate = {2010-12-07/2010-12-10},
    faupublication = {yes},
    isbn = {9784902339215},
    issn = {2165-4727},
    peerreviewed = {Yes},
    title = {An unconventional VNA-based time-domain waveform load-pull test bench},
    type = {Konferenzschrift},
    }

2010

  • S. Leuschner, S. Pinarello, U. Hodel, J. Müller, and H. Klar, "A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages" in Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, 2010. [DOI] [Bibtex]
    @inproceedings{leuschner2010,
    author = {Leuschner, Stephan and Pinarello, Sandro and Hodel, Uwe and Müller, Jan-Erik and Klar, Heinrich},
    booktitle = {Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE},
    cris = {https://cris.fau.de/converis/publicweb/publication/107624044},
    year = {2010},
    month = {05},
    day = {23},
    doi = {10.1109/RFIC.2010.5477401},
    eventdate = {2010-05-23/2010-05-25},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages},
    }

2009

  • S. Pinarello, J. Müller, and R. Weigel, "Geometrical demonstration of the VSWR-locus in different reference planes and its applications" in Microwave Conference, 2009. APMC 2009. Asia Pacific, 2009, pp. 1635-1638. [DOI] [Bibtex]
    @inproceedings{pinarello2009,
    abstract = {When evaluating the RF robustness of a power amplifier test measurements are performed on a locus of load conditions with constant voltage standing wave ratio (VSWR). The reference plane is normally set at the antenna input terminal where this constant VSWR locus of points represented on a Smith chart is a circle centred on the origin: often 50 Ohm. For design and technology purposes this investigation is performed via on wafer measurement at the transistor level, before the matching network. This implies that a different locus has to be chosen. Previous literature approaches this issue in a purely algebraical way which formulates the relationship between this two loci but leaves peculiar properties of the transformation unrevealed and unused. In this paper the problem is geometrically tackled and solved by reasoning on the nature of the loci and on the properties of the functions involved. The geometrical procedure is then arithmetically formalised as a linear system of equations whose solutions are compared with those of the classical approach. This comparison lead to discover an imprecision in the formulas previously published. The geometrical reasoning reveals a set of peculiar solutions which are traced back to conditions on the S-parameters of the matching network. The outcome of this proof is suitable for a software implementation and can be applied to an automated load-pull measurement set-up.},
    author = {Pinarello, Sandro and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {Microwave Conference, 2009. APMC 2009. Asia Pacific},
    cris = {https://cris.fau.de/converis/publicweb/publication/123737724},
    year = {2009},
    month = {12},
    doi = {10.1109/APMC.2009.5384345},
    faupublication = {yes},
    keywords = {S-parameters; VSWR; antenna input terminal; matching network},
    pages = {1635--1638},
    peerreviewed = {unknown},
    title = {Geometrical demonstration of the VSWR-locus in different reference planes and its applications},
    }

2005

  • N. Ceylan, J. Müller, and R. Weigel, "Optimization of EDGE Terminal Power Amplifiers Using Memoryless Digital Predistortion", IEEE Transactions on Microwave Theory and Techniques, vol. 53, iss. 2, pp. 515-522, 2005. [Bibtex]
    @article{ceylan2005,
    abstract = {This paper describes a lookup-table (LUT)-based digital predistortion system usable for enhanced data for global system for mobile evolution (EDGE) handset transmitters. The system is memoryless and capable of improving average efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude. The obtainable efficiency at maximum linear output power is comparable, but at backoffs superior to commercial EDGE power amplifiers (PAs). Minimum system requirements on word length and LUT size have been investigated, which shows that a LUT having approximately 500 coefficients and a system word length of 13 bits are sufficient for EDGE. The proposed system is simple compared to basestation implementations comprising PA memory compensation and can be easily implemented in handsets in order to improve the overall system performance. The effects of antenna mismatch on system performance have been investigated.},
    author = {Ceylan, Nazim and Müller, Jan-Erik and Weigel, Robert},
    publisher = {IEEE},
    cris = {https://cris.fau.de/converis/publicweb/publication/107471364},
    year = {2005},
    month = {02},
    faupublication = {yes},
    issn = {0018-9480},
    journaltitle = {IEEE Transactions on Microwave Theory and Techniques},
    keywords = {linear circuits; mobile communication; power amplifiers; memoryless systems},
    number = {2},
    pages = {515--522},
    peerreviewed = {Yes},
    shortjournal = {IEEE T MICROW THEORY},
    title = {Optimization of EDGE Terminal Power Amplifiers Using Memoryless Digital Predistortion},
    volume = {53},
    }

2004

  • N. Ceylan, J. Müller, and R. Weigel, "A New Addressing Method for LUT Based Digital Predistortion Linearizers" in International Symposium on Signals, Systems, and Electronics (ISSSE), Linz, Austria, 2004. [Bibtex]
    @inproceedings{ceylan2004,
    author = {Ceylan, Nazim and Müller, Jan-Erik and Weigel, Robert},
    booktitle = {International Symposium on Signals, Systems, and Electronics (ISSSE)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123422024},
    year = {2004},
    month = {08},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {A New Addressing Method for LUT Based Digital Predistortion Linearizers},
    venue = {Linz, Austria},
    }
  • N. Ceylan, J. Müller, and R. Weigel, "Optimization of EDGE terminal power amplifiers using memoryless digital predistortion" in Radio Frequency Integrated Circuits Symposium, Fort Worth, TX, USA, 2004, pp. 373-376. [DOI] [Bibtex]
    @inproceedings{ceylan2004a,
    abstract = {This paper describes a look up table (LUT) based digital predistortion system usable for EDGE (enhanced data for GSM evolution) handset transmitters. The system is memoryless and capable of improving system efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude (EVM). Minimum system requirements on wordlength and LUT size have been investigated. It is shown that a LUT having about 500 coefficients and a system wordlength of 13 bits are sufficient for EDGE. The proposed system is simple and can be easily implemented in handsets in order to improve the overall system performance.},
    author = {Ceylan, Nazim and Müller, Jan-Erik and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {Radio Frequency Integrated Circuits Symposium},
    cris = {https://cris.fau.de/converis/publicweb/publication/116335604},
    year = {2004},
    month = {06},
    day = {06},
    doi = {10.1109/RFIC.2004.1320625},
    eventdate = {2004-06-06/2004-06-08},
    faupublication = {yes},
    keywords = {UHF power amplifiers;cellular radio;linearisation techniques;memoryless systems;mobile handsets;radio transmitters;table lookup;13 bit;EDGE handset transmitters;EDGE terminal power amplifiers;EVM;LUT based digital predistortion;LUT size;enhanced data for GSM evolution;error vector magnitude;look up table wordlength;memoryless digital predistortion;offset frequencies leakage power;power amplifier linearization methods;power amplifier optimization;GSM;Linearity;Memoryless systems;Mobile communication;Power amplifiers;Power generation;Predistortion;System performance;Table lookup;Telephone sets},
    pages = {373--376},
    peerreviewed = {Yes},
    title = {Optimization of EDGE terminal power amplifiers using memoryless digital predistortion},
    venue = {Fort Worth, TX, USA},
    }
  • R. Weigel, N. Ceylan, and J. Müller, "Polar Transmitter Linearization with Digital Predistortion" in Proc. European Microwave Conference, Amsterdam, NL, 2004. [Bibtex]
    @inproceedings{weigel2004a,
    author = {Weigel, Robert and Ceylan, Nazim and Müller, Jan-Erik},
    booktitle = {Proc. European Microwave Conference},
    cris = {https://cris.fau.de/converis/publicweb/publication/121852324},
    year = {2004},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {Polar Transmitter Linearization with Digital Predistortion},
    venue = {Amsterdam, NL},
    }

2003

  • N. Ceylan, J. Müller, T. Pittorino, and R. Weigel, "Mobile phone power amplifier linearity and efficiency enhancement using digital predistortion" in Microwave Conference, 2003. 33rd European, Munich, Germany, 2003, pp. 269-272. [DOI] [Bibtex]
    @inproceedings{ceylan2003,
    abstract = {The new generation mobile communication systems using spectrum efficient linear modulation schemes (QPSK, 8PSK, QAM) need linear power amplifiers in the transmission path to have good ACPR and EVM values. Linearization methods can be used to increase the linearity of the power amplifiers (PA). However, it is not reasonable to use complicated, power consuming and high cost systems. This paper presents a digital predistortion implementation for WCDMA signals using an FPGA (field programmable gate array) as DSP and investigates the application of this system in handsets. The method applied requires minimum change in the conventional transmitter path configuration but considerable PAE improvement can be achieved.},
    author = {Ceylan, Nazim and Müller, Jan-Erik and Pittorino, Tindaro and Weigel, Robert},
    publisher = {IEEE},
    booktitle = {Microwave Conference, 2003. 33rd European},
    cris = {https://cris.fau.de/converis/publicweb/publication/121838464},
    year = {2003},
    month = {10},
    doi = {10.1109/EUMC.2003.1262271},
    faupublication = {yes},
    keywords = {8PSK; ACPR; EVM; FPGA DSP; PAE improvement; QAM; QPSK; WCDMA signals; digital predistortion; efficiency enhancement; field programmable gate array; linear power amplifiers; linearity; linearization methods; mobile communication systems; mobile handsets; mobile phone power amplifier linearity; spectrum efficient linear modulation schemes; transmitter path configuration; MMIC power amplifiers; code division multiple access; digital signal processing chips; distortion; field programmable gate arrays; linearisation techniques; mobile handsets; phase shift keying; quadrature amplitude modulation; quadrature phase shift keying},
    pages = {269--272},
    peerreviewed = {unknown},
    title = {Mobile phone power amplifier linearity and efficiency enhancement using digital predistortion},
    venue = {Munich, Germany},
    volume = {1},
    }

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