Staff

M. Sc. Stefan Pechmann

Contact

  • Mail:
  • Phone: 09131/85-27203
  • Fax: 09131/85-28730
  • Room: 03.236
  • Cauerstraße 9
    91058 Erlangen

About Stefan Pechmann

Biography

Stefan Pechmann received the M.Sc. in Electrical Engineering, Electronic and Information Technology from the FAU Erlangen-Nuernberg in April 2018.
Since June 2018 he works as research assistant at the Institute for Electronics Engineering in the Mixed Signal Integrated Circuits Team (MXIC).
His work focuses on integrated Memristor Circuits.

Areas of Interest

  • Memristors
  • analog and mixed-signal circuit design

Open thesis projetcs

Just contact me if you are interested in the topics above. Focus of the thesis can be set depending on your strength and preferences.

Publications

2020

  • M. Völkel, S. Pechmann, H. Jalli Ng, D. Kissinger, R. Weigel, and A. Hagelauer, "An Integrated Bistatic 4TX/4RX Six-Port MIMO-Transceiver at 60 GHz in a 130-nm SiGe BiCMOS Technology for Radar Applications" in International Microwave Symposium, Los Angeles, USA, 2020 (to be published). [Bibtex]
    @inproceedings{voelkel2020,
    abstract = {In this paper, a scalable, fully digital adjustable,
    bistatic 60 GHz MIMO six-port transceiver is presented. The
    circuit features four independent transmitters and four six-port
    receivers on a single chip. The reference clock frequency of
    15 GHz is buffered and multiplied up to 60 GHz. The reference
    clock is also amplified and feed to an output port of the
    chip to render possible cascading multiple chips for massive
    MIMO applications. The receivers each include a VGA to set
    the reference power level, a LNA for amplification of the weak
    antenna signal and the six-port structure with three broadside
    linecoupler, a wilkinson-divider and four power detectors. The
    transmitters each include a switched-line phase shifter and a
    power amplifier. The whole circuit also contains an IQ-modulator
    which offers the opportunity for communication or correlation
    radar in future work. All settings for these components are
    adjusted by a 20 bit serial interface (6 bit address, 14 bit data).
    It is realized in 0.13μm CMOS logic and consists of a shift
    register, decoder and and an analog interface. The chip has a
    size of 4mm x 3.1mm and a power consumption of 960mW
    from a 3.3V power supply. A minimum input power of -22dBm
    is needed at the input clock. The transmitters deliver a maximum
    output power of 9.1dBm at 60 GHz. The phase is adjustable in
    a range from 0 to 325.4. The successful measurement results
    indicate, that the MIMO six-port transceiver is well suited for
    radar applications.
    }, author = {Völkel, Matthias and Pechmann, Stefan and Jalli Ng, Herman and Kissinger, Dietmar and Weigel, Robert and Hagelauer, Amelie}, language = {English}, booktitle = {International Microwave Symposium}, cris = {https://cris.fau.de/converis/publicweb/publication/234017322}, year = {2020}, month = {06}, day = {24}, eventdate = {2020-06-21/2020-06-26}, faupublication = {yes}, keywords = {bistatic,digital adjustable,industrial radar,integrated transceiver; interferometric radar; millimeter wave circuits; Multiple-Input Multiple-Output (MIMO); MMIC; SiGe BiCMOS; scalable; six-port}, note = {unpublished}, peerreviewed = {automatic}, title = {An Integrated Bistatic 4TX/4RX Six-Port MIMO-Transceiver at 60 GHz in a 130-nm SiGe BiCMOS Technology for Radar Applications}, type = {Konferenzschrift}, venue = {Los Angeles, USA}, }

2019

  • M. Völkel, S. Pechmann, E. M. Hussein, D. Kissinger, R. Weigel, and A. Hagelauer, "A Cascadable Integrated Bistatic Six-port Transceiver at 60 GHz in a 130-nm BiCMOS Technology for SIMO-Radar Applications" in APMC, , Singapore, 2019. [Bibtex]
    @inproceedings{voelkel2019e,
    abstract = {In this paper a 60 GHz cascadable bistatic integrated
    interferometric transceiver for SIMO radar applications
    is presented. The integrated transceiver has been designed in a
    0.13μm SiGe BiCMOS technology (SG13G2) from the institute
    innovations for high performance microelectronics (IHP). The
    System includes a 15 GHz buffer stage, a low noise amplifier, a
    passive interferometric six-port structure, several detectors and
    amplifiers as well as a digital interface. The chip has a size
    of 2.75mm x 1.15mm and a maximum power consumption of
    525mW from a 3.3V power supply. The 15 GHz frequency
    input is multiplied to reach a 60 GHz signal at a minimum
    input power of -40 dBm. The chip delivers a maximum output
    power of 10.2 dBm. A digital interface adjusts the output power
    between -22 and 10,2 dBm at an output frequency of 60 GHz. The
    reference input power of the six-port and the RF input power
    could be adjusted in a range of 13.2 dB. The maximum P1dB is at
    -24.1 dBm. The measured power detector sensitivity is 7090 V/W.
    The standard deviation of the phase measurement is 0.025 rad.
    }, author = {Völkel, Matthias and Pechmann, Stefan and Hussein, Eissa Mohamed and Kissinger, Dietmar and Weigel, Robert and Hagelauer, Amelie}, language = {English}, booktitle = {APMC}, cris = {https://cris.fau.de/converis/publicweb/publication/225394716}, year = {2019}, month = {12}, day = {12}, eventdate = {2019-12-10/2019-12-13}, faupublication = {yes}, keywords = {bistatic; industrial radar; integrated transceiver; interferometric radar; millimeter wave circuits; SIMO Radar; MMIC; SiGe BiCMOS; six-port; system-on-chip (SoC)}, peerreviewed = {unknown}, title = {A Cascadable Integrated Bistatic Six-port Transceiver at 60 GHz in a 130-nm BiCMOS Technology for SIMO-Radar Applications}, type = {Konferenzschrift}, venue = {, Singapore}, }

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