Mitarbeiter

Dr.-Ing. Christopher Söll

Kontakt

Über Christopher Söll

Lebenslauf

Christopher Söll wurde 1987 in Naila geboren. Er studierte von 2008 bis 2013 Elektrotechnik, Elektronik und Informationstechnik an der FAU Erlangen-Nürnberg und schloss dies mit Auszeichnung ab. Für seine herausragenden Leistungen während des Studiums wurde er mit dem Deutschland Stipendium, dem Rhode & Schwarz Best Bachelor award und dem Semikron Preis ausgezeichnet. Zurzeit ist er am Lehrstuhl für Technische Elektronik and der FAU Erlangen-Nürnberg angestellt. Sein Forschungsschwerpunkt liegt auf integrierten Analog-/Mixed-Signal Schaltungen und er arbeitet auf seinen Doktortitel im Bereich der analogen Vorverarbeitung für Bildsysteme hin. Außerdem ist er ein Mitglied des IEEE und der IEEE Gesellschaften für "Solid-State Circuits" und "Circuits and Systems".

Arbeitsgebiete

  • Entwurf und Layout von integrierten Analog- und Mixed-Signal-Schaltungen mit Cadence Virtuoso
  • Corner und Monte-Carlo Analysen zur Yield Optimierung mit Virtuoso und WiCkeD
  • Test der Schaltungen am Waferprober
  • Schwerpunkte: Imaging, Signalverarbeitung

Abschlussarbeiten

Bitte melden, falls Interesse an einem der genannten Arbeitsgebiete besteht.

Lehrveranstaltungen Wintersemester 2019

  • Integrierte Schaltungen für Funkanwendungen

Publikationen

2019

  • J. Potschka, C. Söll, J. Kirchner, C. Mardin, M. Stadelmayer, T. Maiwald, S. Breun, K. Kolb, A. Bauch, M. Dietz, C. Beck, M. Völkel, A. Hagelauer, and R. Weigel, "Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process" in IEEE Engineering in Medicine and Biology Conference (EMBC), Berlin, 2019. [Bibtex]
    @inproceedings{potschka2019,
    author = {Potschka, Julian and Söll, Christopher and Kirchner, Jens and Mardin, Christian and Stadelmayer, Markus and Maiwald, Tim and Breun, Sascha and Kolb, Katharina and Bauch, Andreas and Dietz, Marco and Beck, Christopher and Völkel, Matthias and Hagelauer, Amelie and Weigel, Robert},
    booktitle = {IEEE Engineering in Medicine and Biology Conference (EMBC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/217754593},
    year = {2019},
    month = {07},
    day = {23},
    eventdate = {2019-07-23/2019-07-27},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process},
    type = {Konferenzschrift},
    venue = {Berlin},
    }

2018

  • C. Söll, M. Reichenbach, J. Röber, A. Hagelauer, R. Weigel, and D. Fey, "Case Study on Memristor-Based Multilevel Memories", International Journal of Circuit Theory and Applications, vol. 46, iss. 1, pp. 99-112, 2018. [DOI] [Bibtex]
    @article{soell2017,
    abstract = {In this work, the benefits of memristor-based multilevel memories are described along with their design problems. Starting with measurements of discrete actual devices, a discrete memristor based multilevel memory is developed. It uses a printed circuit board in order to connect eight packaged memristors from Bio Inspired to test a ternary Arithmetic Logic Unit (ALU) on a field programmable gate array (FPGA). These circuits are then integrated in the second proposed memory system based on a 150nm CMOS process that can be equipped with memristors on top of the metal layers. This integrated solution includes proper read-out, erase and write circuits to control real memristors, and 32x32 memristive memory cells. It is compared to a common static random-access memory (SRAM) in terms of area, computation speed and power consumption showing benefits for memory sizes bigger than 70 words. Since yield and device variations are still a big issue in memristor fabrication, methods to counter these problems are also proposed in the end. An actual implementation should offer several trimming solutions to ensure proper functionality of a prototype memory as well as a power-on calibration, until these problems are solved. The development of the presented memories is not only based on different models but also measurements done with real devices.},
    author = {Söll, Christopher and Reichenbach, Marc and Röber, Jürgen and Hagelauer, Amelie and Weigel, Robert and Fey, Dietmar},
    publisher = {Wiley Online Library},
    cris = {https://cris.fau.de/converis/publicweb/publication/108239824},
    year = {2018},
    month = {01},
    doi = {10.1002/CTA.2379},
    faupublication = {yes},
    issn = {0098-9886},
    journaltitle = {International Journal of Circuit Theory and Applications},
    keywords = {Memristor; Multi-Level Memory; Memory Interface; Memristive Computing; GRK-1773},
    number = {1},
    pages = {99--112},
    peerreviewed = {Yes},
    shortjournal = {INT J CIRC THEOR APP},
    title = {Case Study on Memristor-Based Multilevel Memories},
    type = {Article in Journal},
    volume = {46},
    }

2017

  • D. Wust, M. Biglari, J. Knödtel, M. Reichenbach, C. Söll, and D. Fey, "Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment" in Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on, Thessaloniki, Greece, 2017, pp. 1-7. [DOI] [Bibtex]
    @inproceedings{wust2017a,
    abstract = {
    Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom designs. The testing environment is comprised of two main components: a dedicated hardware interface circuit for steering discrete memristor devices and a memory controller as IP core establishing the communication with the hardware interface utilizing an easy-to-use AXI interface. Furthermore, in order to integrate the prototyping platform in processing systems a C API is supplied. This testing environment lays the foundation for integrating memristors in future hybrid CMOS-based SoCs. The platform is put into practice for evaluating a ternary processor on physical hardware using memristors as multi-level storage cells.
    }, author = {Wust, Daniel and Biglari, Mehrdad and Knödtel, Johannes and Reichenbach, Marc and Söll, Christopher and Fey, Dietmar}, language = {English}, publisher = {IEEE}, booktitle = {Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on}, cris = {https://cris.fau.de/converis/publicweb/publication/119528024}, year = {2017}, month = {09}, day = {25}, doi = {10.1109/PATMOS.2017.8106978}, eventdate = {2017-09-25/2017-09-27}, eventtitle = {International Symposium on Power and Timing Modeling, Optimization and Simulation}, faupublication = {yes}, isbn = {9781509064625}, keywords = {memristor test platform; memristive computing; FPGA; off-the-shelf devices}, pages = {1--7}, peerreviewed = {Yes}, title = {Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment}, type = {Journal Article}, url = {http://ieeexplore.ieee.org/document/8106978/}, venue = {Thessaloniki, Greece}, }
  • C. Söll, J. Röber, H. Milosiu, R. Weigel, and A. Hagelauer, "Area-Efficient Fully Integrated Dual-Band Class-E/F Power Amplifier with Switchable Output Power for a BPSK/OOK Transmitter" in IEEE International Symposium on Circuits and Systems, Baltimore, USA, 2017, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{soell2017a,
    abstract = {This paper presents a novel area-efficient dual-band class-E/F power amplifier (PA) with switchable output power. It is targeted to work in a BPSK/OOK transmitter in smart facility applications like an autarkic asset-tracking system based on small sensor nodes. The amplifier is able to operate at both 434MHz and 868MHz without the need for additional inductors. The output power settings at 868MHz are controllable between -1.79dBm and -24.61dBm at 4.96mA and 1.43mA current consumption, respectively. The whole circuit including all inductors and the matching network in front of the antenna consumes only 0.9mm2 chip area and is fully integrated in a 180nm CMOS process together with a VCO and a PLL.},
    author = {Söll, Christopher and Röber, Jürgen and Milosiu, Heinrich and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {IEEE International Symposium on Circuits and Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/108242684},
    year = {2017},
    doi = {10.1109/ISCAS.2017.8050676},
    faupublication = {yes},
    keywords = {Class-E/F Power Amplifier; Dual-Band; Switchable Output Power; Asset-Tracking System},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Area-Efficient Fully Integrated Dual-Band Class-E/F Power Amplifier with Switchable Output Power for a BPSK/OOK Transmitter},
    type = {Konferenzschrift},
    venue = {Baltimore, USA},
    }
  • D. Wust, C. Söll, and D. Fey, "A fast general purpose CPU utilizing signed-digit encoding and multi-bit memristors" in HiPEAC Workshop on Memristor Technology, Design, Automation and Computing, 2017. [Bibtex]
    @inproceedings{wust2017,
    abstract = {-},
    author = {Wust, Daniel and Söll, Christopher and Fey, Dietmar},
    booktitle = {HiPEAC Workshop on Memristor Technology, Design, Automation and Computing},
    cris = {https://cris.fau.de/converis/publicweb/publication/122912724},
    year = {2017},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {A fast general purpose CPU utilizing signed-digit encoding and multi-bit memristors},
    }

2016

  • D. Fey, M. Reichenbach, C. Söll, M. Biglari, J. Röber, and R. Weigel, "Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits" in Proceedings of the Second International Symposium on Memory Systems, Alexandria, VA, USA, 2016, pp. 442-454. [DOI] [Bibtex]
    @inproceedings{fey2016a,
    abstract = {

    Signed-digit (SD) arithmetic exploits positive and negative digits requiring more than two states. It is long known that an addition using trits, i.e. each digit stores not only a 0 or a 1 but also either 2 or -1, requires only a constant number of steps independent of the operands' word length. However, current processors could not profit from that due to the lack of fast, dense and CMOS compatible memory cells that can store reliably multiple states. Memristors offer these features making it necessary to re-evaluate different SD number representations and to evaluate the consequences of an implementation of a multi-value register file with memristors concerning latency, area and energy consumption.

    Using memristors as multi-value register reduces latency and area on one side compared to flip-flop based memories. On the other side this requires additional sophisticated control circuitry to implement ADCs/DACs, current limiting circuits and to generate control signals to read, write and erase memristors. The paper determines the break-even points at which ternary circuits attached to memristor based registers show better energy-delay products and less area consumption and how much power consumption these improvements cost. By layout synthesis is shown that ternary adders with trit-storing memristors can reduce the latency for a word length of 16 digits about 19% and about 52% for 512 digits compared to a binary carry-look-ahead (CLA) adder with nearly the same power consumption.

    }, author = {Fey, Dietmar and Reichenbach, Marc and Söll, Christopher and Biglari, Mehrdad and Röber, Jürgen and Weigel, Robert}, language = {English}, publisher = {ACM}, booktitle = {Proceedings of the Second International Symposium on Memory Systems}, cris = {https://cris.fau.de/converis/publicweb/publication/108131584}, year = {2016}, month = {10}, day = {03}, doi = {10.1145/2989081.2989124}, eventdate = {2016-10-03/2016-10-06}, eventtitle = {The International Symposium on Memory Systems (MEMSYS)}, faupublication = {yes}, isbn = {9781450343053}, keywords = {Signed-digit arithmetic multi-bit memristors memristive computing; multi-bit memristors; memristive computing; GRK}, pages = {442--454}, peerreviewed = {Yes}, title = {Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits}, type = {Journal Article}, url = {https://dl.acm.org/citation.cfm?id=2989124}, venue = {Alexandria, VA, USA}, }
  • L. Shi, M. Berger, B. Bier, C. Söll, J. Röber, R. Fahrig, B. Eskofier, A. Maier, and J. Maier, "Analog Non-Linear Transformation-Based Tone Mapping for Image Enhancement in C-arm CT" in IEEE Medical Imaging Conference (MIC), Strasbourg, France, 2016. [Bibtex]
    @inproceedings{shi2016a,
    abstract = {Flat-Panel C-arm Computed Tomography (CT) suffers from pixel saturation due to the detector’s limited dynamic range. We describe a novel approach to analog, non-linear tone mapping (TM) for preventing detector saturation. An analog TM operator (TMO) applies a non-linear transformation in a CMOS sensor and its inverse TMO based on 14-bit digital raw data. This is done in order to prevent overexposure and to enhance image quality to 32 bits. The method was applied to the cases of low-contrast head imaging and to that of imaging both knees. Cone-beam projection data with and without overexposure was simulated for a 200° short-scan of the knees and a 360° full-scan of a Forbild head phantom. The results show an increased correlation coefficient of 0.99 compared to 0.96 for overexposed knee data and a higher low-contrast visibility (CC=0.99) compared to linear quantization (CC=0.97).},
    author = {Shi, Lan and Berger, Martin and Bier, Bastian and Söll, Christopher and Röber, Jürgen and Fahrig, Rebecca and Eskofier, Björn and Maier, Andreas and Maier, Jennifer},
    booktitle = {IEEE Medical Imaging Conference (MIC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/109689624},
    year = {2016},
    month = {10},
    faupublication = {yes},
    keywords = {GRK-1773},
    peerreviewed = {Yes},
    title = {Analog Non-Linear Transformation-Based Tone Mapping for Image Enhancement in C-arm CT},
    venue = {Strasbourg, France},
    }
  • C. Söll, L. Shi, J. Röber, M. Reichenbach, R. Weigel, and A. Hagelauer, "Low-Power Analog Smart Camera Sensor for Edge Detection" in IEEE International Conference on Image Processing (ICIP), Phoenix, USA, 2016. [DOI] [Bibtex]
    @inproceedings{soell2016,
    abstract = {This work presents an intelligent analog image sensor system for smart camera applications with the need of edge or marker detection. The system consists of a 3x3 read-out CMOS image sensor, an analog Sobel stage and additional circuitry like operational amplifiers and comparators to compute a 1bit image with the edges present in the taken photo. This information can then be further processed digitally to detect specific shapes in order to control robot routines, for example. The architecture of the proposed system is highly desirable as dedicated analog hardware has significant advantages in terms of power and speed compared to digital implementations. The overall system is simulated with the help of a 3x3 CMOS image sensor IC as well as Cadence Virtuoso for analog circuit simulation and MATLAB to convert the sequential information back to an image, and compared to other state of the art CMOS image sensors with edge detection capability. The analog Sobel circuit runs with a clock of 10MHz and consumes less than 0.79mW average power for the computation of the example image, and the whole 200x200 pixel image sensor consumes only 5.5mW at a frame rate of 75 fps.},
    author = {Söll, Christopher and Shi, Lan and Röber, Jürgen and Reichenbach, Marc and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {IEEE International Conference on Image Processing (ICIP)},
    cris = {https://cris.fau.de/converis/publicweb/publication/123903164},
    year = {2016},
    month = {09},
    doi = {10.1109/ICIP.2016.7533193},
    faupublication = {yes},
    keywords = {Smart Camera; CMOS Image Sensor; Analog Processing Circuits; Analog Sobel; GRK-1773},
    peerreviewed = {Yes},
    title = {Low-Power Analog Smart Camera Sensor for Edge Detection},
    venue = {Phoenix, USA},
    }
  • C. Söll, T. Mai, L. Shi, J. Röber, T. Ußmüller, R. Weigel, and A. Hagelauer, "Low-Power High-Gain Operational Amplifier for Analog Image Pre-Processing in Smart Sensor Systems" in 15. ITG/GMM-Fachtagung Analog 2016, Bremen, 2016, pp. 28-32. [Bibtex]
    @inproceedings{soell2016c,
    abstract = {In this work, a low-power high-gain operational amplifier is presented, which is dedicated to work in an analog image pre-processing stage in a smart sensor system. This stage is able to detect edges and shapes for instance, before the image is passed to the ADC and the digital computation stage, reducing data and precision requirement of both stages. This approach helps to save power, making smart image sensor nodes with energy harvesting reasonable. Since the precision as well as the energy consumption of the edge detection algorithm is highly depended on the amplifier used for the basic summing and multiplier blocks, the design of it plays an important role for the approach. The proposed input/output rail-to-rail operational amplifier is based on a 150 nm CMOS process, has a gain of 77 dB and a unity gain bandwidth of 45.7MHz while consuming only 77 µA statically at a supply voltage of 1.8V.},
    author = {Söll, Christopher and Mai, Timo and Shi, Lan and Röber, Jürgen and Ußmüller, Thomas and Weigel, Robert and Hagelauer, Amelie},
    booktitle = {15. ITG/GMM-Fachtagung Analog 2016},
    cris = {https://cris.fau.de/converis/publicweb/publication/122848044},
    year = {2016},
    month = {09},
    faupublication = {yes},
    isbn = {9783800742653},
    keywords = {analog pre-processing; operational amplifier; low-power; high-gain; folded-cascode; GRK-1773},
    pages = {28--32},
    peerreviewed = {Yes},
    title = {Low-Power High-Gain Operational Amplifier for Analog Image Pre-Processing in Smart Sensor Systems},
    venue = {Bremen},
    }
  • L. Shi, D. Hadlich, C. Söll, T. Ußmüller, and R. Weigel, "A Tone Mapping Algorithm Suited for Analog-Signal Real-Time Image Processing" in 12th International Conference on PhD Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, 2016. [DOI] [Bibtex]
    @inproceedings{shi2016,
    abstract = {This work presents a Tone Mapping Operator (TMO) which adjusts the High Dynamic Range (HDR) of image sensor data to the limited dynamic range of conventional displays with analog signal processing. It is based on Photographic Tone Reproduction (PTR) and suitable for analog circuit design in a CMOS image sensor in order to reduce the hardware cost and operation time for real-time image processing. For this reason, the characteristic advantage and calculation limitation of analog technology are considered in the TMO algorithm proposal. Furthermore, the appropriate modelling is built and simulated in Verilog-A. The function of the algorithm is feasible for analog processing. The frequency of the analog TMO is upper 52MHz while it consumes 55mW. The simulation results of test images are compared with the digital global TMO and the proposed analog TMO provides a reasonable similar dynamic range compression.},
    author = {Shi, Lan and Hadlich, David and Söll, Christopher and Ußmüller, Thomas and Weigel, Robert},
    booktitle = {12th International Conference on PhD Research in Microelectronics and Electronics (PRIME)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122827584},
    year = {2016},
    month = {06},
    doi = {10.1109/PRIME.2016.7519457},
    faupublication = {yes},
    keywords = {Image Processing; Tone Mapping; CMOS Image Sensor; Analog Circuit; GRK 1773},
    peerreviewed = {Yes},
    title = {A Tone Mapping Algorithm Suited for Analog-Signal Real-Time Image Processing},
    venue = {Lisbon, Portugal},
    }
  • A. Steg, M. Reichenbach, C. Söll, L. Shi, A. Maier, and C. Riess, "Dynamic Pixel Binning allows Spatial and Angular Resolution Tradeoffs to improve Image Quality in X-Ray C-Arm CT" in IEEE International Symposium on Biomedical Imaging (ISBI), Prague, 2016, pp. 577-580. [DOI] [Bibtex]
    @inproceedings{steg2016,
    abstract = {When designing an acquisition protocol for a C-arm CT acquisition, a tradeoff has to be made between scan time and the amount of acquired data. If the scan is increased, data of spatially and angular higher resolution can be acquired. If the scan time is fixed, one has to tradeoff spatial and angular resolution, which may either lead to oversmoothing or artifacts from angular undersampling. In this work, we investigate the viability of smart cameras for pushing the boundary for this bottleneck considerably further. The detector pixels are enhanced by processing units that are able to perform a limited amount of local operations. This allows an online, dynamical adaptation of the pixel binning, depending on whether a local neighborhood is smooth or not. We demonstrate on phantom data that this approach allows to save about 75% of the data, obtaining a reconstruction quality comparable to 1 x 1 binning at a data rate comparable to 2 x 2 pixel binning.},
    author = {Steg, Alexander and Reichenbach, Marc and Söll, Christopher and Shi, Lan and Maier, Andreas and Riess, Christian},
    booktitle = {IEEE International Symposium on Biomedical Imaging (ISBI)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122837044},
    year = {2016},
    month = {04},
    doi = {10.1109/ISBI.2016.7493334},
    faupublication = {yes},
    keywords = {Pixel Binning; X-ray detector; C-arm reconstruction; Dynamic Pixel Binning; X-ray C-arm CT},
    pages = {577--580},
    peerreviewed = {Yes},
    title = {Dynamic Pixel Binning allows Spatial and Angular Resolution Tradeoffs to improve Image Quality in X-Ray C-Arm CT},
    venue = {Prague},
    }
  • D. Fey, M. Reichenbach, C. Söll, and R. Weigel, "Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors" in HIPEAC Workshop on Memristor Technology, Design, Automation and Computing, Prague, 2016, pp. 1-6. [Bibtex]
    @inproceedings{fey2016,
    abstract = {Signed-digit (SD) arithmetic, e.g. ternary computer arithmetic circuits process trits instead of bits. It is long known that trits, which are using for each digit not only 0 and 1but in addition either 2 or -1, can carry out an addition in a constant number of steps independent of the used word length of the operands. However, corresponding SD arithmetic circuits have not been used in current processors so far due to the missing of fast, dense and CMOS compatible memory cells that can store reliably multiple levels. Memristors offer these features making necessary a re-evaluation of different SD number representations and their corresponding arithmetic circuits realized in CMOS technology. In addition appropriate analogue-to-digital (A/D) and digital-to-analogue (D/A) interfaces between digital CMOS circuits and multi-level memristors are ne-cessary and have to be considered in this investigation. The paper evaluates different SD number represen-tations using digits with three or five levels for the adder. It is concluded that an SD addition using trits and three elementary processing steps is currently the best solution for memristors. This solution is currently implemented in a first hardware demonstrator using commercially available memristor devices, discretely realised A/D and D/A converters which link the memristor registers to an FPGA implementing the SD arithmetic.},
    author = {Fey, Dietmar and Reichenbach, Marc and Söll, Christopher and Weigel, Robert},
    booktitle = {HIPEAC Workshop on Memristor Technology, Design, Automation and Computing},
    cris = {https://cris.fau.de/converis/publicweb/publication/120004984},
    year = {2016},
    month = {01},
    faupublication = {yes},
    keywords = {Memristor; GRK-1773},
    pages = {1--6},
    peerreviewed = {Yes},
    title = {Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors},
    venue = {Prague},
    }
  • L. Shi, C. Söll, B. Pfundt, A. Bänisch, M. Reichenbach, J. Seiler, T. Ussmueller, and R. Weigel, "A flexible mixed-signal image processing pipeline using 3D chip stacks", Journal of Real-Time Image Processing, vol. 14, iss. 3, pp. 517-534, 2016. [DOI] [Bibtex]
    @article{shi2016b,
    abstract = {This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera applications. These systems need to fit different constraints regarding power consumption, speed and quality, and the optimal compromise may differ depending on the application. Moreover, the best implementation of a desired image processing task may be in the analog or the digital domain, or even a combined computation. Different aspects starting from the image sensor and signal acquisition up to the pre-processing in analog and digital domain are investigated in this paper to optimize not just one part of the system, but the whole system altogether. Moreover, it is shown that analog processing algorithms can improve signal quality, processing speed and latency while being able to save power, which is important for real-time systems. In order to be able to carry out spatial operations, the state-of-the-art sensor is modified to be able to read out multiple pixels at the same time. This allows analog spatial filter operations which consume significantly less power. As an example, an averaging filter is described which needs less than 5.3 % of the power–time product of a digital implementation for one computation. To enhance data throughput and flexibility, 3D chip stacking is proposed to partition the sensor in smaller units and enable massively parallel processing.},
    author = {Shi, Lan and Söll, Christopher and Pfundt, Benjamin and Bänisch, Andreas and Reichenbach, Marc and Seiler, Jürgen and Ussmueller, Thomas and Weigel, Robert},
    publisher = {Springer Verlag (Germany)},
    cris = {https://cris.fau.de/converis/publicweb/publication/106120564},
    year = {2016},
    doi = {10.1007/S11554-016-0628-5},
    faupublication = {yes},
    issn = {1861-8200},
    journaltitle = {Journal of Real-Time Image Processing},
    keywords = {3D chip stacking; Analog pre-processing; Application optimized image pipeline; Partitioning; Smart camera},
    number = {3},
    pages = {517--534},
    peerreviewed = {Yes},
    shortjournal = {J REAL-TIME IMAGE PR},
    title = {A flexible mixed-signal image processing pipeline using 3D chip stacks},
    type = {Article in Journal},
    volume = {14},
    }

2015

  • C. Söll, L. Shi, A. Bänisch, T. Ußmüller, and R. Weigel, "A CMOS Image Sensor with Analog Pre-Processing Capability Suitable for Smart Camera Applications" in IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Bali, Indonesia, 2015, pp. 279-284. [DOI] [Bibtex]
    @inproceedings{soell2015b,
    abstract = {This work presents a novel CMOS sensor which is suitable for analog image processing operations and describes the benefits of analog pre-processing over digital algorithms. All needed modifications to read out a spatial NxN pixel matrix simultaneously are presented regarding pixel wiring, row decoder and column multiplexer as well as descrambling the order of the outputs. The outputs are connected via a buffer stage to the analog pre-processing circuits. As an example for such an analog computation, an averaging filter is described from design constraints to the actual implementation. Simulation results show a very low current consumption of just 55.3 µA under worst-case conditions and a computation time below 200 ns. This corresponds to a power-time product ratio of 1:18.75 compared to a digital state-of-the-art implementation.},
    author = {Söll, Christopher and Shi, Lan and Bänisch, Andreas and Ußmüller, Thomas and Weigel, Robert},
    booktitle = {IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108075704},
    year = {2015},
    month = {11},
    doi = {10.1109/ISPACS.2015.7432780},
    faupublication = {yes},
    keywords = {Smart Cameras; CMOS Image Sensors; Analog Processing Circuits; Filtering Algorithms; GRK-1773},
    pages = {279--284},
    peerreviewed = {Yes},
    title = {A CMOS Image Sensor with Analog Pre-Processing Capability Suitable for Smart Camera Applications},
    venue = {Bali, Indonesia},
    }
  • C. Lindner, C. Söll, J. Röber, A. Bänisch, and R. Weigel, "Yield Analysation and Optimization Methods for Active CMOS Pixels" in 8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Siegen, Germany, 2015, pp. 107-114. [Bibtex]
    @inproceedings{lindner2015b,
    abstract = {This work explains how to simulate error sources in image sensors to analyze yield. Moreover, two circuitry-wise methods to reduce these interferences are proposed and their influences on yield and standard deviation caused by process variations and reset noise are analyzed. Thereby the biggest sources of interference within the pixel architectures are described. After comparing three different pixel architectures, their extracted layout is simulated and the results are compared. Especially the change of the yield and the standard deviation with and without the use of DS and CDS are analyzed. By applying the methods mentioned before the yield could be increased by up to 15.6 %.},
    author = {Lindner, Claus and Söll, Christopher and Röber, Jürgen and Bänisch, Andreas and Weigel, Robert},
    booktitle = {8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122818124},
    year = {2015},
    month = {09},
    faupublication = {yes},
    isbn = {9783800740710},
    keywords = {Yield Analysis; Active Cmos Pixel; Image Sensor; Correlated Double Sampling; Double Sampling; Simulation Method; GRK-1773},
    pages = {107--114},
    peerreviewed = {Yes},
    title = {Yield Analysation and Optimization Methods for Active CMOS Pixels},
    venue = {Siegen, Germany},
    }
  • C. Söll, L. Shi, A. Bänisch, J. Röber, T. Ußmüller, and R. Weigel, "Analog Computation Methods with the help of analog and pseudo-digital Carry Signals" in IEEE European conference on circuit theory and design (ECCTD), Trondheim, 2015, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{soell2015a,
    abstract = {This work describes new methods of handling exceedings of the supply range in analog computation stages. These are handled as pseudo-digital and analog carry signals and used to regulate the gain of the stage where they occur as well as all computation stages that follow. A complete example for such an analog computation is simulated and presented and critical parts of the architectures are addressed. In addition, more sophisticated extensions are proposed and the ”right” way of carry handling is explained for a specific algorithm, together with a discussion of the advantages of different methods for each application.},
    author = {Söll, Christopher and Shi, Lan and Bänisch, Andreas and Röber, Jürgen and Ußmüller, Thomas and Weigel, Robert},
    booktitle = {IEEE European conference on circuit theory and design (ECCTD)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108075484},
    year = {2015},
    month = {08},
    doi = {10.1109/ECCTD.2015.7300039},
    faupublication = {yes},
    keywords = {analog computation; analog carry; pseudo-digital carry; pre-processing; GRK-1773},
    pages = {1--4},
    peerreviewed = {Yes},
    title = {Analog Computation Methods with the help of analog and pseudo-digital Carry Signals},
    venue = {Trondheim},
    }
  • C. Söll, A. Bänisch, J. Röber, L. Shi, and R. Weigel, "A Multi-Functional Reconfigurable Low-Power Ultra-High PSRR CMOS Reference-System" in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, 2015, pp. 220-223. [DOI] [Bibtex]
    @inproceedings{soell2015,
    abstract = {This paper presents a new reference system with emphasis on low power design and high power supply rejection. The untrimmed reference provides a 600mV output voltage, which only differs by 5.75mV in the temperature range between -40 ° C and +125 ° C and a PSRR of -157.2 dB at 10Hz. The core part of the reference produces a reference potential of 416.1mV with a deviation of only 1.59mV. Moreover, the circuit provides a 900mV output, a temperature independent 3 µA current and trimming possibilities for the temperature curves and the amplitude of output voltages and currents. Under all operating conditions, the post-layout Corner- and Monte-Carlo-Simulations show a power consumption of less than 40 µA and ensure functionality across process, supply voltage and temperature variations.},
    author = {Söll, Christopher and Bänisch, Andreas and Röber, Jürgen and Shi, Lan and Weigel, Robert},
    booktitle = {IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)},
    cris = {https://cris.fau.de/converis/publicweb/publication/108045124},
    year = {2015},
    month = {06},
    doi = {10.1109/PRIME.2015.7251374},
    faupublication = {yes},
    keywords = {bandgap; reference; low power; high psrr; temperature coefficient; subregulation; GRK-1773},
    pages = {220--223},
    peerreviewed = {Yes},
    title = {A Multi-Functional Reconfigurable Low-Power Ultra-High PSRR CMOS Reference-System},
    venue = {Glasgow},
    }
  • B. Pfundt, M. Reichenbach, D. Fey, and C. Söll, "Novel Image Processing Architecture for 3D Integrated Circuits" in Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), Potsdam, 2015, pp. 5-15. [Bibtex]
    @inproceedings{pfundt2015,
    abstract = {Utilizing highly parallel processors for high speed embedded image processing is a well known approach. However, the question of how to provide a sufficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nevertheless, the usage of a new technology requires architectural changes in the processing units.With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was developed in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 30.000 fps (frames per second) for 5x5 filters.},
    author = {Pfundt, Benjamin and Reichenbach, Marc and Fey, Dietmar and Söll, Christopher},
    booktitle = {Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/124219964},
    year = {2015},
    month = {05},
    faupublication = {yes},
    keywords = {3D IC; TSV; parallel processing; 2D filters; full buffering},
    pages = {5--15},
    peerreviewed = {Yes},
    title = {Novel Image Processing Architecture for 3D Integrated Circuits},
    venue = {Potsdam},
    }
  • L. Shi, C. Söll, A. Bänisch, R. Weigel, J. Seiler, and T. Ußmüller, "Concept for a CMOS Image Sensor Suited for Analog Image Pre-Processing" in DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems, Grenoble, France, 2015, pp. 16-21. [Bibtex]
    @inproceedings{shi2015a,
    abstract = {A concept for a novel CMOS image sensor suited for analog image pre-processing is presented in this paper. As an example, an image restoration algorithm for reducing image noise is applied as image pre-processing in the analog domain. To supply low-latency data input for analog image preprocessing, the proposed concept for a CMOS image sensor offers a new sensor signal acquisition method in 2D. In comparison to image pre-processing in the digital domain, the proposed analog image pre-processing promises an improved image quality. Furthermore, the image noise at the stage of analog sensor signal acquisition can be used to select the most effective restoration algorithm applied to the analog circuit due to image processing prior to the A/D converter.},
    author = {Shi, Lan and Söll, Christopher and Bänisch, Andreas and Weigel, Robert and Seiler, Jürgen and Ußmüller, Thomas},
    language = {English},
    booktitle = {DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/106361904},
    year = {2015},
    month = {03},
    day = {13},
    eventdate = {2015-03-13/2015-03-13},
    eventtitle = {Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems},
    faupublication = {yes},
    pages = {16--21},
    peerreviewed = {Yes},
    title = {Concept for a CMOS Image Sensor Suited for Analog Image Pre-Processing},
    venue = {Grenoble, France},
    }

2014

  • J. Walk, J. Kolpak, C. Söll, R. Weigel, G. Fischer, and T. Ußmüller, "Remote powered medical implants for Telemonitoring (Invited Paper)", Proceedings of the IEEE, vol. 102, iss. 10, pp. 100-116, 2014. [DOI] [Bibtex]
    @article{walk2014,
    abstract = {Chronicle diseases like diabetes mellitus often need a permanent monitoring of vital signs. Especially the use of telemedicine might increase the quality of life for concerned patients. New systems are required which permanently detect and provide health status information. But, these systems must not control patient’s life and shall work autonomous. For this purpose, intelligent medical implants are well qualified. The present work describes a system for wireless power supply and communication with medical implant applications. Monitoring vital signs might lead to a big amount of data. Therefore, high data rates are necessary provided by high operating frequencies. High frequencies in turn lead to high attenuation losses because of the frequency dependent relative permittivity $\epsilon_r$ of the human body. Hence, high frequencies are not suitable for energy transfer through the human body. The presented concept is based on two different frequencies for power supply and data transmission. An independent devel- opment of both blocks is possible. The power supply operates on 13.56 MHz using inductive coupling. Thereby, the human body doesn’t affect the energy transfer. In contrast, the data transmission is operated by a frequency of the Medical Implant Communication Service band. The elaborated system consists of an power supply unit, a data transmission unit and a control unit. The implementation of the power supply and data transmission as well as associated theoretical basics are presented. Performed measurements demonstrate that the realized system is qualified for the use on human beings.},
    author = {Walk, Jasmin and Kolpak, Jasmin and Söll, Christopher and Weigel, Robert and Fischer, Georg and Ußmüller, Thomas},
    publisher = {IEEE},
    cris = {https://cris.fau.de/converis/publicweb/publication/123397604},
    year = {2014},
    month = {10},
    doi = {10.1109/JPROC.2014.2359517},
    faupublication = {yes},
    issn = {0018-9219},
    journaltitle = {Proceedings of the IEEE},
    keywords = {biological tissues; biomedical communication; biomedical power supplies; energy storage; frequency domain analysis; implantable biomedical devices; permittivity},
    number = {10},
    pages = {100--116},
    peerreviewed = {Yes},
    shortjournal = {P IEEE},
    title = {Remote powered medical implants for Telemonitoring (Invited Paper)},
    volume = {102},
    }

2012

  • C. Söll, J. Walk, G. Fischer, R. Weigel, and T. Ußmüller, "Implantable Antenna for Medical Sensor Platforms" in 19th International Conference on Microwave, Radar and Wireless Communications (MIKON), Warsaw, 2012, pp. 402-405. [DOI] [Bibtex]
    @inproceedings{soell2012,
    author = {Söll, Christopher and Walk, Jasmin and Fischer, Georg and Weigel, Robert and Ußmüller, Thomas},
    booktitle = {19th International Conference on Microwave, Radar and Wireless Communications (MIKON)},
    cris = {https://cris.fau.de/converis/publicweb/publication/120545744},
    year = {2012},
    month = {05},
    doi = {10.1109/MIKON.2012.6233487},
    faupublication = {yes},
    pages = {402--405},
    peerreviewed = {unknown},
    title = {Implantable Antenna for Medical Sensor Platforms},
    venue = {Warsaw},
    }

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