Mitarbeiter

Dr.-Ing. Vadim Issakov

Kontakt

Lehrveranstaltungen Sommersemester 2019

Preise & Auszeichnungen

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, RWW Student Paper Competition, 2nd place, IEEE Radio and Wireless Week, 2019. [Bibtex]
    @prize{ciocoveanu_prize_2019,
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    booktitle = {IEEE Radio and Wireless Week},
    cris = {ciocoveanu_prize_2019},
    year = {2019},
    month = {01},
    day = {22},
    title = {RWW Student Paper Competition, 2nd place},
    type = {20773-Kleiner Preis},
    }

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Publikationen

2020

  • S. Breun, S. Kehl-Waas, and V. Issakov, "Extended Equivalent Circuit Model for Enhanced Substrate Modeling of Three-Port Inductors" in RWW 2020, 2020 (to be published). [Bibtex]
    @inproceedings{breun2020,
    abstract = {This paper presents an extension to the equivalent circuit of a three-port inductor model which enhances the quality factor accuracy by precisely considering the parasitic substrate losses caused by eddy current effects. The proposed equivalent circuit allows to correctly model the broadband frequency dependency of the substrate admittances. Furthermore it is applied to an almost fully analytical extraction procedure and can therefore be used for the generation of scalable inductor models.
    }, author = {Breun, Sascha and Kehl-Waas, Sebastian and Issakov, Vadim}, language = {English}, booktitle = {RWW 2020}, cris = {https://cris.fau.de/converis/publicweb/publication/227024935}, year = {2020}, month = {01}, day = {26}, eventdate = {2020-01-26/2020-01-29}, faupublication = {yes}, note = {unpublished}, peerreviewed = {automatic}, title = {Extended Equivalent Circuit Model for Enhanced Substrate Modeling of Three-Port Inductors}, }
  • S. Breun, M. Völkel, A. Schrotz, M. Dietz, V. Issakov, and R. Weigel, "A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with -178 dBc/Hz FOMT" in RWW 2020, 2020 (to be published). [Bibtex]
    @inproceedings{breun2020a,
    abstract = {This paper presents a low-power wideband push-push voltage controlled oscillator (VCO), achieving a frequency tuning-range (FTR) of 19 GHz (14 %) at a center frequency of 136 GHz. The VCO yields a minimum phase noise of −86.5 dBc/Hz at 1 MHz offset at a power consumption of around 27 mW from a 1.8 V supply, which yields a FOMT of −178 dBc/Hz. The chip is fabricated using a 130 nm SiGe BiCMOS technology with ft/fmax of 250 GHz/370 GHz, respectively, and is integrated with a by-32 divider chain attached to the fundamental output of the VCO, offering a 2.1 GHz output for an external phaselocked loop (PLL).
    }, author = {Breun, Sascha and Völkel, Matthias and Schrotz, Albert-Marcel and Dietz, Marco and Issakov, Vadim and Weigel, Robert}, language = {English}, booktitle = {RWW 2020}, cris = {https://cris.fau.de/converis/publicweb/publication/227024522}, year = {2020}, month = {01}, day = {26}, eventdate = {2020-01-26/2020-01-29}, faupublication = {yes}, note = {unpublished}, peerreviewed = {automatic}, title = {A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with -178 dBc/Hz FOMT}, }

2019

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "A 20.7% PAE 3-Stage 60 GHz Power Amplifier for Radar Applications in 28 nm Bulk CMOS" in European Microwave Week, Paris, France, 2019. [Bibtex]
    @inproceedings{ciocoveanu2019a,
    abstract = {This paper presents a highly efficient 3-stage differential Class-B power amplifier (PA) for short range radar applications, realized in a 28nm bulk CMOS technology. Measurement results show a saturated output power (Psat) of 11.9dBm with a 20.7% power-added efficiency (PAE) at 60 GHz. Moreover, the measurements show that for a frequency range from 57 GHz to 64 GHz, the Psat varies from 10.5dBm to 11.2dBm and the circuit draws 26mA from a 0.9V power supply. Furthermore, the fabricated chip has an area of 0.61mm x 0.31mm including the pads.
    }, author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim}, language = {English}, booktitle = {European Microwave Week}, cris = {https://cris.fau.de/converis/publicweb/publication/220911836}, year = {2019}, month = {12}, day = {29}, eventdate = {2019-09-29/2019-10-04}, faupublication = {yes}, keywords = {Differential PA,60 GHz,28nm CMOS,High Efficiency.}, peerreviewed = {unknown}, title = {A 20.7% PAE 3-Stage 60 GHz Power Amplifier for Radar Applications in 28 nm Bulk CMOS}, type = {Konferenzschrift}, venue = {Paris, France}, }
  • V. Issakov, R. Ciocoveanu, R. Weigel, A. Geiselbrechtinger, and J. Rimmelspacher, "Highly-Integrated Low-Power 60 GHz Multichannel Transceiver for Radar Applications in 28 nm CMOS" in IEEE MTT-S International Microwave Symposium Digest, Boston, MA, USA, 2019, pp. 650-653. [Bibtex]
    @inproceedings{issakov2019,
    abstract = {We present a highly-integrated low-power 60 GHz multi-channel transceiver realized in a 28 nm bulk CMOS technology. The circuit integrates three receive (RX) and two transmit (TX) channels. A receive channel includes an LNA, a passive mixer and a transimpedance amplifier (TIA), while a transmit channel contains a three-stage transformer-coupled differential power amplifier (PA). Additionally, the transceiver integrates a local oscillator (LO) signal generation network comprising a voltage-controlled oscillator (VCO), LO buffers, power splitters, frequency divider and a passive distribution network. The VCO is realized as a push-push cross-coupled topology and is continuously tunable in the frequency range 57-to-72 GHz, while achieving a measured phase noise of -84 dBc/Hz at 1 MHz offset at 60 GHz. The entire transceiver dissipates 342 mW using a single 0.9 V supply. A single RX channel draws 33 mA, while a single TX consumes 43 mA. The circuit including pads occupies a chip area of only 1.9 mm × 2.5 mm, which is limited only by the separation necessary for isolation between the channels. The transceiver provides a competitive performance and is suitable for 60 GHz continuous-wave radar applications.},
    author = {Issakov, V. and Ciocoveanu, Radu and Weigel, Robert and Geiselbrechtinger, A. and Rimmelspacher, J.},
    publisher = {Institute of Electrical and Electronics Engineers Inc.},
    booktitle = {IEEE MTT-S International Microwave Symposium Digest},
    cris = {https://cris.fau.de/converis/publicweb/publication/224167772},
    year = {2019},
    month = {06},
    day = {01},
    eventdate = {2019-06-02/2019-06-07},
    eventtitle = {2019 IEEE MTT-S International Microwave Symposium, IMS 2019},
    faupublication = {yes},
    isbn = {9781728113098},
    issn = {0149-645X},
    journaltitle = {IEEE MTT-S International Microwave Symposium Digest},
    keywords = {CMOS; radar; transceiver},
    pages = {650--653},
    peerreviewed = {unknown},
    title = {Highly-Integrated Low-Power 60 GHz Multichannel Transceiver for Radar Applications in 28 nm CMOS},
    venue = {Boston, MA, USA},
    volume = {2019-June},
    }
  • E. Aguilar, V. Issakov, and R. Weigel, "Highly-Integrated <0.14 mm2D-Band Receiver Front-Ends for Radar and Imaging Applications in a 130 nm SiGe BiCMOS Technology" in 2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019, Orlando, FL, USA, 2019. [DOI] [Bibtex]
    @inproceedings{aguilar2019,
    abstract = {Two low-power D-band receiver front-ends with competitive performance for radar and imaging applications are presented. The receivers include passive and active singleended-to-differential converters realized as an ultra-compact Marchand-based balun and as a differential-pair-based active balun, respectively. The receivers achieve measured conversion gains (CG) of 24.9dB at 134GHz (active balun) and 20.27dB at 124GHz (passive balun) while consuming 425mW and 330mW correspondingly. A wide bandwidth of 32GHz is achieved for the active variant in the 114-146GHz frequency range while the passive approach achieves a CG > 10dB in the 112-147GHz frequency range. The passive approach achieves a peak conversion gain of 20.27dB at 126GHz. The presented results offer competitive performance and compare favorably to reported receiver front-ends in terms of ultra-small silicon area (0.14 and 0.1mm 2 ). The front-ends are suitable for integration in highly-integrated D-Band radar receiver arrays as well as for high-density imaging arrays.},
    author = {Aguilar, Erick and Issakov, Vadim and Weigel, Robert},
    publisher = {Institute of Electrical and Electronics Engineers Inc.},
    booktitle = {2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019},
    cris = {https://cris.fau.de/converis/publicweb/publication/219407077},
    year = {2019},
    month = {05},
    day = {07},
    doi = {10.1109/SIRF.2019.8709129},
    eventdate = {2019-01-20/2019-01-23},
    eventtitle = {19th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019},
    faupublication = {yes},
    isbn = {9781538659502},
    keywords = {active balun; D-band; imaging; passive balun; radar; SiGe; wideband receiver},
    peerreviewed = {unknown},
    title = {Highly-Integrated <0.14 mm2D-Band Receiver Front-Ends for Radar and Imaging Applications in a 130 nm SiGe BiCMOS Technology},
    venue = {Orlando, FL, USA},
    }
  • J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "LC Tank Differential Inductor-Coupled Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology" in Radio & Wireless Week (RWW): Silicon Monolithic Inegrated Circuits in RF Systems (SiRF), Orlando, FL, USA, 2019. [Bibtex]
    @inproceedings{rimmelspacher2019,
    abstract = {This paper presents a 60 GHz dual-core push-push VCO in a 45 nm partially depleted (PD) RF Silicon-on-Insulator (SOI) CMOS technology. The cores are coupled inductively via differential inductors. The best measured phase noise at 1 MHz offset from a 63 GHz carrier is −94.4 dBc/Hz. The wideband continuous frequency-tuning-range (FTR) is 16 %. The DC power dissipation is 76 mW including fundamental 30 GHz and second harmonic (H2) 60 GHz output buffers at 1 V power supply voltage. The measurement results of a reference single-core VCO design proves the relative phase noise improvement of the implemented core-coupling technique. The chip area excluding pads is 0.09 mm2.
    }, author = {Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim}, language = {English}, booktitle = {Radio & Wireless Week (RWW): Silicon Monolithic Inegrated Circuits in RF Systems (SiRF)}, cris = {https://cris.fau.de/converis/publicweb/publication/203768203}, year = {2019}, month = {04}, day = {20}, eventdate = {2019-01-20/2019-01-23}, faupublication = {yes}, keywords = {millimeter-wave VCO,wideband,silicon-on-insulator,CMOS technology,System-on-Chip}, peerreviewed = {unknown}, title = {LC Tank Differential Inductor-Coupled Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology}, type = {Konferenzschrift}, venue = {Orlando, FL, USA}, }
  • J. Rimmelspacher, A. Werthof, R. Weigel, A. Geiselbrechtinger, and V. Issakov, "Experimental Considerations on Accurate fT and fmax Extraction for MOS Transistors Measured up to 110 GHz" in Automated RF Techniques Group (ARFTG) Microwave Measurement Symposium, Orlando, FL, USA, 2019. [Bibtex]
    @inproceedings{rimmelspacher2019a,
    author = {Rimmelspacher, Johannes and Werthof, Andreas and Weigel, Robert and Geiselbrechtinger, Angelika and Issakov, Vadim},
    booktitle = {Automated RF Techniques Group (ARFTG) Microwave Measurement Symposium},
    cris = {https://cris.fau.de/converis/publicweb/publication/209910998},
    year = {2019},
    month = {03},
    day = {20},
    eventdate = {2019-01-20/2019-01-23},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {Experimental Considerations on Accurate fT and fmax Extraction for MOS Transistors Measured up to 110 GHz},
    type = {Konferenzschrift},
    venue = {Orlando, FL, USA},
    }
  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS" in IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Orlando, FL, USA, 2019. [Bibtex]
    @inproceedings{ciocoveanu2019,
    abstract = {This paper presents a 60GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power (Pmax) of 15.3dBm with a competitive maximum power-added efficiency (PAEmax) of 30.5% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8V supply and the chip core size is 0.36mm x 0.35 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/204681005},
    year = {2019},
    month = {01},
    day = {20},
    eventdate = {2019-01-20/2019-01-23},
    faupublication = {yes},
    keywords = {Power Amplifier,High-Power,High-Efficiency,PD-SOI.},
    peerreviewed = {unknown},
    title = {A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {Orlando, FL, USA},
    }
  • V. Issakov, S. Kehl-Waas, and S. Breun, "Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors", IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 66, iss. 9, pp. 3557-3570, 2019. [DOI] [Bibtex]
    @article{issakov2019a,
    abstract = {This paper presents a new, almost fully analytical methodology for component value extraction of a double-π equivalent circuit model for three-port on-chip inductors from a given S-parameter dataset. The compact model provides an accurate fit over a wide frequency range from dc to beyond the self-resonance frequency (SRF) to a tabular input S-parameter model describing a symmetric center-tapped on-chip inductor. The input dataset may be obtained from a measurement or from an electromagnetic field solver simulation. Using a passive broadband equivalent circuit instead of the original S-parameters' description is advantageous for circuit design, as it facilitates the convergence of transient simulations. The proposed approach carefully considers center-tap parasitics. Hence, the obtained equivalent circuit model fits the input inductor characteristics accurately not only for differential excitation but also in the common-mode and single-ended operation. Due to the fact that the proposed extraction approach is based on physical assumptions and analytical circuit decomposition, the obtained component values are physically meaningful and relate to geometry. Thus, this approach is suitable for the generation of scalable compact models, which can be used to speed-up inductor optimization during the RF circuit design. The proposed methodology has been verified on a three-port inductor realized in a 28-nm CMOS technology and measured up to 60 GHz. The extracted equivalent circuit model exhibits an accurate fit to the measured data over the entire frequency range in all operation modes. Finally, field-solver models are used to verify the scalability.
    }, author = {Issakov, Vadim and Kehl-Waas, Sebastian and Breun, Sascha}, cris = {https://cris.fau.de/converis/publicweb/publication/227025706}, year = {2019}, doi = {10.1109/TCSI.2019.2926737}, faupublication = {yes}, issn = {1549-8328}, journaltitle = {IEEE Transactions on Circuits and Systems I-Regular Papers}, keywords = {circuit optimisation;CMOS integrated circuits;equivalent circuits;inductors;integrated circuit modelling;multiport networks;network analysis;radiofrequency integrated circuits;S-parameters;input inductor characteristics;analytical circuit decomposition;analytical equivalent circuit extraction procedure;component value extraction;double-π equivalent circuit model;self-resonance frequency;symmetric center-tapped on-chip inductor;passive broadband equivalent circuit;center-tap parasitics;Broadband Scalable Modeling;three-port center-tapped symmetric on-chip inductors;S-parameter dataset;electromagnetic field solver simulation;single-ended operation;common-mode operation;transient simulations;CMOS technology;Integrated circuit modeling;Inductors;Equivalent circuits;Analytical models;Scattering parameters;Geometry;Numerical models;Equivalent circuit;on-chip inductor;center-tap}, number = {9}, pages = {3557--3570}, peerreviewed = {Yes}, shortjournal = {IEEE T CIRCUITS-I}, title = {Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors}, volume = {66}, }

2018

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, A. Geiselbrechtinger, and V. Issakov, "5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS" in 5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS, Kyoto International Conference Center, Kyoto, Japan, Japan, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018c,
    abstract = {This paper presents a single-stage stacked Class AB power amplifier (PA) with lower complexity for fifth generation (5G) K/Ka band front-ends that has been realized in a 45nm PDSOI CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 17.3 dBm with a 39.7% maximum power-added efficiency (PAEmax) at 24 GHz. The output-referred 1-dB compression point (OP1dB) is 14.3dBm and the saturated output power varies from 15.9dBm to 17.3dBm for a frequency range from 22 GHz to 28 GHz. Furthermore, the circuit draws 40mA from a 2.9V supply and the chip core size is 0.35mm x 0.25 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Geiselbrechtinger, Angelika and Issakov, Vadim},
    language = {English},
    booktitle = {5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS},
    cris = {https://cris.fau.de/converis/publicweb/publication/203983358},
    year = {2018},
    month = {12},
    day = {15},
    eventdate = {2018-11-06/2018-11-09},
    eventtitle = {2018 Asia-Pacific Microwave Conference (APMC 2018)},
    faupublication = {yes},
    keywords = {Stacked PA; 45nm PD-SOI; 5G; High Power; High Efficiency},
    peerreviewed = {unknown},
    title = {5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {Kyoto International Conference Center, Kyoto, Japan, Japan},
    }
  • J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with -101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and -187 dBc/Hz FoMT" in European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018d,
    abstract = {This paper presents a 60 GHz Quad-Core push-push VCO in 45 nm partially depleted Silicon-on-Insulator (SOI) CMOS. The measured phase noise (PN) at 60.5 GHz is −101.7 dB/Hz at 1 MHz offset from carrier. The continuous frequency-tuning range (FTR) is 19 %. The Quad-Core VCO consumes only 40 mW DC power. The complete circuit including fundamental and second harmonic (H2) output buffers draws 110 mA from a single 1 V supply. The VCO cores are coupled via resonant-tank transformers. A similar transformer-coupled Dual-Core VCO is fabricated and measured to prove the relative PN improvement between Dual-Core and Quad-Core topology. The total area of the Quad-Core VCO excluding pads is 0.1 mm2.},
    author = {Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    booktitle = {European Solid-State Circuits Conference (ESSCIRC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/200493727},
    year = {2018},
    month = {12},
    day = {01},
    eventdate = {2018-09-03/2018-09-06},
    faupublication = {yes},
    keywords = {millimeter-wave,wideband,silicon-on-insulator,CMOS technology,System-on-Chip},
    peerreviewed = {unknown},
    title = {A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with -101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and -187 dBc/Hz FoMT},
    type = {Konferenzschrift},
    venue = {Dresden, Germany},
    }
  • J. Rimmelspacher, R. Weigel, and V. Issakov, "A 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology for Integrated Phased-Array Radar Applications" in PHAROS Event, Bordeaux, France, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018e,
    abstract = {This paper presents a 60 GHz push-push voltage-controlled oscillator (VCO) for millimetre-wave (mm-wave) radar applications. The VCO is fabricated in a 45 nm partially-depleted (PD) RF silicon-on-insulator (RF-SOI) CMOS technology. The measured frequency tuning range (FTR) is 15% (56.6 – 65.7 GHz), lowest phase noise (PN) is −91.3 dBc/Hz at 1 MHz offset and the total DC power consumption is 68 mW for a 1 V supply voltage. The simulated core DC power consumption is 10 mW. },
    author = {Rimmelspacher, Johannes and Weigel, Robert and Issakov, Vadim},
    booktitle = {PHAROS Event},
    cris = {https://cris.fau.de/converis/publicweb/publication/210258393},
    year = {2018},
    month = {12},
    day = {07},
    eventdate = {2018-12-05/2018-12-07},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {A 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology for Integrated Phased-Array Radar Applications},
    venue = {Bordeaux, France},
    }
  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS" in A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS, San Diego, California, USA, USA, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018b,
    abstract = {This paper presents a wideband digitally tunable SPST switch based on the travelling-wave concept that has been realized in a 22 nm FD-SOI CMOS technology. The digital control for return loss is performed through mutual inductance switching. Small-signal measurement results show that the proposed SPST switch achieves a bandwidth of 10-110 GHz, with an insertion loss of 1.2 dB at 60 GHz and a 24 dB isolation at 60 GHz, whereas large-signal measurements show a 1-dB compression point of +7 dBm at 24 GHz. Furthermore, the 3 digital control bits allow tuning return loss center frequency by approximately 7 GHz. The chip core size is 0.12 mm x 0.15 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS},
    cris = {https://cris.fau.de/converis/publicweb/publication/203983033},
    year = {2018},
    month = {11},
    day = {15},
    eventdate = {2018-10-14/2018-10-17},
    eventtitle = {2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {San Diego, California, USA, USA},
    }
  • J. Rimmelspacher, S. Breun, A. Werthof, A. Geiselbrechtinger, R. Weigel, and V. Issakov, "Experimental Comparison of Integrated Transformers in a 28 nm Bulk CMOS Technology" in European Microwave Conference 2018, Madrid, Spain, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018b,
    abstract = {This paper presents a systematic comparison of integrated transformer structures realized in a 28 nm bulk CMOS technology and characterized up to the millimetre-wave frequencies. First, the rectangular versus octagonal coil shapes are compared. Next, different transformer routing realizations using various magnetic coupling mechanisms are examined: interleaved transformers using lateral coupling, stacked ones using vertical coupling and symmetrical transformers using the combination of both coupling mechanisms. Finally, the comparison is repeated for different turn ratios: 1:1, 1:2 and 2:2. The electrical properties of the transformers, such as self-inductance, quality factor, self-resonance frequencies and mutual coupling coefficient are analysed. Advantages and disadvantages of these structures are discussed with regard to their applicability in various active circuits. One of the main targets is to obtain the best transformer’s electrical parameters for a given fixed area and given metallization option. The structures are measured up to 70 GHz. On-chip interconnects are de-embedded and the devices are compared to the models simulated by EM field solver.
    }, author = {Rimmelspacher, Johannes and Breun, Sascha and Werthof, Andreas and Geiselbrechtinger, Angelika and Weigel, Robert and Issakov, Vadim}, booktitle = {European Microwave Conference 2018}, cris = {https://cris.fau.de/converis/publicweb/publication/200127203}, year = {2018}, month = {09}, day = {25}, eventdate = {2018-09-25/2018-09-27}, faupublication = {no}, keywords = {millimeter-wave,CMOS,transformers}, peerreviewed = {unknown}, title = {Experimental Comparison of Integrated Transformers in a 28 nm Bulk CMOS Technology}, type = {Konferenzschrift}, venue = {Madrid, Spain}, }
  • J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "60 GHz Tail-Node-Coupled Multi-Core Push-Push VCOs in 22 nm FD SOI CMOS Technology" in European Microwave Conference 2018, Madrid, Spain, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018c,
    abstract = {This paper proposes a compact realization of a phase-noise (PN) improving core-coupling technique for millimetre-wave (mm-Wave) CMOS LC voltage-controlled oscillators (VCOs). The target is to provide a multi-core wideband continuous frequency-tuning-range (FTR) and low PN for FMCW radar applications while maintaining area and complexity at a minimum level. The VCO cores are superharmonic injection-locked at second harmonic (H2) on a common tail node. Three VCOs are fabricated in a 22 nm fully depleted (FD) silicon-on-insulator (SOI) CMOS technology: Single-Core, Dual-Core and Quad-Core. All implementations have the same core design. Measurements show the expected PN improvement for the multi-core VCOs compared to the single-core VCO.},
    author = {Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    booktitle = {European Microwave Conference 2018},
    cris = {https://cris.fau.de/converis/publicweb/publication/111630244},
    year = {2018},
    month = {09},
    day = {25},
    eventdate = {2018-09-25/2018-09-27},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {60 GHz Tail-Node-Coupled Multi-Core Push-Push VCOs in 22 nm FD SOI CMOS Technology},
    venue = {Madrid, Spain},
    }
  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "Bias-switched Down-Conversion Mixer for Flicker Noise Reduction in 28-nm CMOS" in Texas Symposium on Wireless and Microwave Circuits and Systems, Waco, Texas, USA, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018a,
    abstract = {This paper presents a modified Gilbert-cell mixer employing a novel biasing-scheme used to reduce the high Noise Figure, due to inherently high 1/f noise of MOS transistors. Switching the transistor from strong inversion to accumulation interferes with the self-correlation of the physical noisy process, which leads to a reduction in flicker noise. To illustrate this improvement, a comparison with a conventionally biased mixer is carried. Post-layout simulation results show that this mixer achieves a voltage conversion gain of 2.2 dB, a 1 dB compression point of 3 dBm and a 5 dB reduction in noise figure at 50 kHz, while it draws a current of 13 mA from a single 0.9 V supply. The occupied chip area is 0.5x0.94 mm². According to author’s knowledge this is the first time that bias switching technique is applied to a mixer at mm-wave frequencies.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {Texas Symposium on Wireless and Microwave Circuits and Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/200465469},
    year = {2018},
    month = {07},
    day = {01},
    eventdate = {2018-04-05/2018-04-06},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {Bias-switched Down-Conversion Mixer for Flicker Noise Reduction in 28-nm CMOS},
    type = {Konferenzschrift},
    venue = {Waco, Texas, USA},
    }
  • V. Issakov, A. Werthof, J. Rimmelspacher, R. Weigel, and A. Geiselbrechtinger, "Experimental Study on Crosstalk Reduction between Integrated Inductors up to Millimeter-Wave Regime" in 91st ARFTG Microwave Measurement Conference (ARFTG), Philadelphia, PA, USA, 2018. [Bibtex]
    @inproceedings{issakov2018a,
    abstract = {Amount of inductors and transformers in highly integrated mm-wave multi-channel data communication and radar transceivers is steadily increasing with the growing complexity of the chips. Driven on one hand by higher integration of phased-array transceivers, e.g., for 5G applications, yet on the other hand by the demand for cost and chip area reduction, inductors need to be placed densely close to each other. This causes unwanted interferences coupled via inductors between different parts of the integrated system, resulting in SNR degradation, reduced data rates and nonlinear distortion effects. This paper presents an experimental study on coupling between on-chip inductors and investigation of various crosstalk reduction techniques for highly integrated SoCs up to mm-wave frequencies. We compare different orientations of 8-shaped inductors and discuss a rotated version of the 8-shape coil, which provides an additional improvement of 10 dB over the entire frequency range. Two-port measurements of coupled inductors connected single-endedly are performed up to 145 GHz. Additionally, 4-port measurements are done up to 70 GHz. We propose analyzing the crosstalk mechanisms by converting the measured S-parameters into the mixed-mode representation. Test structures were realized in 28 nm bulk CMOS technology node.},
    author = {Issakov, Vadim and Werthof, Andreas and Rimmelspacher, Johannes and Weigel, Robert and Geiselbrechtinger, Angelika},
    booktitle = {91st ARFTG Microwave Measurement Conference (ARFTG)},
    cris = {https://cris.fau.de/converis/publicweb/publication/210258726},
    year = {2018},
    month = {06},
    day = {10},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {Experimental Study on Crosstalk Reduction between Integrated Inductors up to Millimeter-Wave Regime},
    type = {Journal Article},
    venue = {Philadelphia, PA, USA},
    }
  • J. Rimmelspacher, A. Hagelauer, R. Weigel, and V. Issakov, "A 60 GHz Push-Push Voltage-Controlled Oscillator with Adaptive Gate Biasing in 28 nm Bulk CMOS Technology" in International Microwave Symposium 2018, Philadelphia, Pennsylvania, USA, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018a,
    author = {Rimmelspacher, Johannes and Hagelauer, Amelie and Weigel, Robert and Issakov, Vadim},
    booktitle = {International Microwave Symposium 2018},
    cris = {https://cris.fau.de/converis/publicweb/publication/119625704},
    year = {2018},
    month = {06},
    day = {10},
    eventdate = {2018-06-10/2018-06-15},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {A 60 GHz Push-Push Voltage-Controlled Oscillator with Adaptive Gate Biasing in 28 nm Bulk CMOS Technology},
    type = {Konferenzschrift},
    venue = {Philadelphia, Pennsylvania, USA},
    }
  • R. Ciocoveanu, J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS" in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Anaheim, USA, 2018, pp. 19-22. [DOI] [Bibtex]
    @inproceedings{ciocoveanu2018,
    abstract = {
    This paper presents a high linearity modified Gilbert-cell mixer designed for 60-GHz applications and fabricated in a 28-nm CMOS technology. To increase the linearity of the mixer, the RF transconductance stage was removed, thereby reducing the amount of stacked transistors. We propose using a self-biasing Vth reference in the bias network to make the mixer more robust to process-voltagetemperature (PVT) variations. Measurement results show that this mixer achieves a voltage conversion gain of 4.7 dB, a 1-dB compression point of -3 dBm and a 12.3 dB noise figure, while it draws only 2 mA from a single 0.9 V supply. The occupied area on the chip is 0.35x0.68 mm2 including pads.
    }, author = {Ciocoveanu, Radu and Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim}, language = {English}, booktitle = {Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems}, cris = {https://cris.fau.de/converis/publicweb/publication/111716704}, year = {2018}, month = {01}, day = {14}, doi = {10.1109/SIRF.2018.8304218}, eventdate = {2018-01-14/2018-01-17}, faupublication = {yes}, keywords = {Down-Conversion Mixer,High-Linearity,Low-Power,PVT Robust}, pages = {19--22}, peerreviewed = {unknown}, title = {A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS}, type = {Konferenzschrift}, venue = {Anaheim, USA}, }
  • J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "30 % Frequency-Tuning-Range 60 GHz Push-Push VCO in 28 nm Bulk CMOS Technology" in Radio & Wireless Week 2018, Anaheim, California, USA, USA, 2018. [DOI] [Bibtex]
    @inproceedings{rimmelspacher2018,
    abstract = {This paper presents a 60 GHz push-push crosscoupled voltage-controlled oscillator (VCO) in 28 nm bulk CMOS technology. It achieves a continuous frequency tuning range (FTR) of 30% from 52 to 71 GHz in a single sweep. We propose coupling the fundamental harmonic from the VCO core by means of magnetic coupling via a transformer-based resonant tank. This is used instead of directly connecting the output buffers to the oscillation node. The VCO provides a phase noise in the range of -93 to -82 dBc/Hz at 1 MHz offset from carrier across the entire FTR. The measured DC power dissipation including buffers at the fundamental and second harmonic outputs does not exceed 68 mW. The circuit operates from a single supply of 0.9 V. The circuit area excluding pads is 0.15 mm2. Thanks to the achieved very wide continuous FTR, the presented VCO is suitable for FMCW radar applications that require a very fine range resolution.},
    author = {Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {Radio & Wireless Week 2018},
    cris = {https://cris.fau.de/converis/publicweb/publication/107729864},
    year = {2018},
    month = {01},
    day = {14},
    doi = {10.1109/SIRF.2018.8304221},
    eventdate = {2018-01-14/2018-01-18},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {30 % Frequency-Tuning-Range 60 GHz Push-Push VCO in 28 nm Bulk CMOS Technology},
    venue = {Anaheim, California, USA, USA},
    }

2017

  • J. Rimmelspacher, A. Hagelauer, R. Weigel, and V. Issakov, "Experimental Study of Injected Interference Effects on Modulated Sidebands in CMOS LC VCO" in International Conference on Microwaves, Communications, Antennas and Electronic Systems, Tel-Aviv, Israel, 2017, pp. 1-4. [DOI] [Bibtex]
    @inproceedings{rimmelspacher2017a,
    abstract = {This paper presents an experimental study on modulated sidebands in the output spectrum of a millimeterwave (mm-wave) CMOS voltage controlled oscillator (VCO). The results are used to calculate the injected current into the resonant tank in dependency on its locking range. The evaluated parameters are a measure of the oscillator’s sensitivity regarding injected periodic interferences. This is of interest when implemented in highly integrated systems, as e.g. in system-on-chip solutions.},
    author = {Rimmelspacher, Johannes and Hagelauer, Amelie and Weigel, Robert and Issakov, Vadim},
    language = {English},
    booktitle = {International Conference on Microwaves, Communications, Antennas and Electronic Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/111498024},
    year = {2017},
    month = {11},
    day = {13},
    doi = {10.1109/COMCAS.2017.8244812},
    eventdate = {2017-11-13/2017-11-15},
    faupublication = {yes},
    keywords = {injection locking,injection pulling,interference,modulated sidebands,millimeter-wave oscillator,CMOS technolog},
    pages = {1--4},
    peerreviewed = {unknown},
    title = {Experimental Study of Injected Interference Effects on Modulated Sidebands in CMOS LC VCO},
    type = {Journal Article},
    venue = {Tel-Aviv, Israel},
    }
  • V. Issakov, J. Rimmelspacher, S. Trotta, M. Tiebout, A. Hagelauer, and R. Weigel, "A 52-to-67 GHz Dual-Core Push-Push VCO in 40-nm CMOS" in European Microwave Conference, Nuremberg, Germany, 2017, pp. 755-758. [DOI] [Bibtex]
    @inproceedings{issakov2017a,
    abstract = {

    We present a continuously tunable 52-to-67 GHz push-push dual-core voltage-controlled oscillator (VCO) in a 40 nm bulk CMOS technology. The circuit is suitable for 60 GHz FMCW radar applications requiring a continuously tunable ultra-wide modulation bandwidth. The LC-tank inductor is used to couple the two VCO cores. The fundamental frequency of the VCO can be tuned from 26 GHz to 33,5 GHz, which corresponds to a frequency tuning range (FTR) of 25%. The second harmonic is extracted in a non-invasive way using a transformer. The primary side acts simultaneously as a second harmonic filter. The VCO achieves in measurement a low phase noise of 91,8 dBc=Hz at 1 MHz offset at 62 GHz and an output power of 20 dBm. The VCO including buffers dissipates in the dual-core operation mode 60 mA from a single 1,1 V supply and consumes a chip area of 0,58 mm2.}, author = {Issakov, Vadim and Rimmelspacher, Johannes and Trotta, Saverio and Tiebout, Marc and Hagelauer, Amelie and Weigel, Robert}, language = {English}, booktitle = {European Microwave Conference}, cris = {https://cris.fau.de/converis/publicweb/publication/111491424}, year = {2017}, month = {10}, day = {08}, doi = {10.23919/EUMC.2017.8230957}, eventdate = {2017-10-08/2017-10-13}, eventtitle = {European Microwave Conference}, faupublication = {yes}, keywords = {millimeter-wave,ultra-wideband,CMOS technology}, pages = {755--758}, peerreviewed = {Yes}, title = {A 52-to-67 GHz Dual-Core Push-Push VCO in 40-nm CMOS}, type = {Journal Article}, venue = {Nuremberg, Germany}, }

  • V. Issakov, J. Rimmelspacher, A. Werthof, A. Hagelauer, and R. Weigel, "Experimental Study on Substrate Coupling in Bulk Silicon and RF-SOI CMOS up to 110 GHz" in IEEE MTT-S International Microwave Symposium 2017, Honolulu, Hawaii, USA, USA, 2017, p. 3. [DOI] [Bibtex]
    @inproceedings{issakov2017,
    abstract = {Interferences injected to an RF circuit may strongly deteriorate the electrical performance. Parasitic coupling via substrate is one of the dominant interference transmission mechanisms in highly integrated systems. The effect of substrate coupling becomes more critical at higher circuit frequencies. This poses a particular challenge for highly integrated millimeterwave systems, since isolation techniques become less efficient with an increasing operating frequency. This paper presents an experimental study on coupling via bulk silicon and RFSOI substrates. We investigate in measurement up to 110 GHz efficiency of several isolation techniques, such as triple-well, p+ and n+ guard-rings and use of undoped highly resistive region. Additionally, RF-SOI substrates are known to be beneficial for higher crosstalk isolation. However, also this isolation degrades at higher frequencies. Hence, we investigate in measurement up to 110 GHz the isolation via low-resistivity and high-resistivity trap-rich SOI substrate variants. Test structures were realized in 40 nm bulk CMOS and 45 nm RF-SOI technology nodes.},
    author = {Issakov, Vadim and Rimmelspacher, Johannes and Werthof, Andreas and Hagelauer, Amelie and Weigel, Robert},
    language = {English},
    booktitle = {IEEE MTT-S International Microwave Symposium 2017},
    cris = {https://cris.fau.de/converis/publicweb/publication/108607444},
    year = {2017},
    month = {06},
    day = {04},
    doi = {10.1109/MWSYM.2017.8058792},
    eventdate = {2017-06-04/2017-06-09},
    eventtitle = {International Microwave Symposium 2017},
    faupublication = {yes},
    keywords = {millimeter-wave,Substrate-coupling effects,CMOS,Silicon-on-Insulator.},
    pages = {3},
    peerreviewed = {unknown},
    title = {Experimental Study on Substrate Coupling in Bulk Silicon and RF-SOI CMOS up to 110 GHz},
    type = {Journal Article},
    venue = {Honolulu, Hawaii, USA, USA},
    }
  • J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "36 % Frequency-Tuning-Range Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology" in IEEE MTT-S International Microwave Symposium 2017, Honolulu, HI, USA, 2017, pp. 1356-1358. [DOI] [Bibtex]
    @inproceedings{rimmelspacher2017,
    abstract = {This paper presents a millimeter-wave (mm-wave) push-push voltage-controlled oscillator (VCO) in a 45 nm RFSOI CMOS technology. The circuit aims to meet specifications for FMCW radar applications requiring an ultra-wide PLL modulation bandwidth. The fundamental output of the VCO can be tuned from 27 GHz to 39 GHz, which corresponds to frequency tuning range (FTR) of 36 %. We extract the 2nd harmonic in a non-invasive way using a transformer. The measured phase noise (PN) at 1 MHz offset from the fundamental carrier varies across the tuning range from -100 dBc/Hz to -90 dBc/Hz. The VCO including output buffers dissipates 65 mW DC power from a single 1 V supply and consumes a chip area of 0.12 mm2.},
    author = {Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {IEEE MTT-S International Microwave Symposium 2017},
    cris = {https://cris.fau.de/converis/publicweb/publication/111456664},
    year = {2017},
    month = {06},
    day = {04},
    doi = {10.1109/MWSYM.2017.8058865},
    eventdate = {2017-06-04/2017-06-09},
    eventtitle = {International Microwave Symposium 2017},
    faupublication = {yes},
    keywords = {millimeter-wave,ultra-wideband,CMOS technology,cutoff frequency,System-on-Chip,Silicon-on-Insulator},
    pages = {1356--1358},
    peerreviewed = {unknown},
    title = {36 % Frequency-Tuning-Range Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology},
    type = {Journal Article},
    venue = {Honolulu, HI, USA},
    }

2016

  • V. Issakov, M. Wojnowski, H. Knapp, S. Trotta, H. Forstner, K. Pressel, and A. Hagelauer, "Co-simulation and Co-design of Chip-Package-Board Interfaces in Highly-Integrated RF Systems" in IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), New Brunswick, NJ, USA, 2016, pp. 94-101. [DOI] [Bibtex]
    @inproceedings{issakov2016,
    abstract = {The level of integration for RF and mm-wave systems is continuously increasing. Highly-integrated system on chip solutions have to be encapsulated in a package and assembled on a board. In addition, to be more attractive as a product, the trend goes towards further integration of passives and antennas in a package. This drives the system in package solutions. However, electrical properties of the package and board may have a significant effect on system parameters, especially at high frequencies. Hence, layout features of package and board must be carefully modelled and considered during the design. Furthermore, it is often insufficient to model chip, package and board separately, as some high-frequency effects may not be captured. An example is electromagnetic coupling between integrated coils on chip and routing traces in package. In this paper we describe considerations on co-simulation and co-design of highlyintegrated RF systems by means of accurate electromagnetic modelling. We demonstrate the approach and various aspects of chip-package-board co-design based on examples of systems for various applications: 6 GHz VCO using embedded inductor; backhaul communication system in package for V-band and Eband and a four-channel 77 GHz automotive radar transceiver in a package with four dipole antennas.},
    author = {Issakov, Vadim and Wojnowski, Maciej and Knapp, Herbert and Trotta, Saverio and Forstner, Hans-Peter and Pressel, Klaus and Hagelauer, Amelie},
    publisher = {IEEE},
    booktitle = {IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)},
    cris = {https://cris.fau.de/converis/publicweb/publication/124176184},
    year = {2016},
    month = {09},
    day = {25},
    doi = {10.1109/BCTM.2016.7738959},
    eventdate = {2016-09-25/2016-09-27},
    faupublication = {yes},
    pages = {94--101},
    peerreviewed = {Yes},
    title = {Co-simulation and Co-design of Chip-Package-Board Interfaces in Highly-Integrated RF Systems},
    venue = {New Brunswick, NJ, USA},
    }

2012

  • M. Wojnowski, V. Issakov, G. Knoblinger, K. Pressel, G. Sommer, and R. Weigel, "High-Q Inductors Embedded in the Fan-Out Area of an eWLB", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, iss. 8, pp. 1280-1292, 2012. [DOI] [Bibtex]
    @article{wojnowski2012,
    abstract = {We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package.},
    author = {Wojnowski, Maciej and Issakov, Vadim and Knoblinger, G. and Pressel, Klaus and Sommer, Grit and Weigel, Robert},
    publisher = {IEEE},
    cris = {https://cris.fau.de/converis/publicweb/publication/108587424},
    year = {2012},
    month = {03},
    doi = {10.1109/TCPMT.2012.2186963},
    faupublication = {yes},
    issn = {2156-3950},
    journaltitle = {IEEE Transactions on Components, Packaging and Manufacturing Technology},
    keywords = {Microwave measurements; packaging; passive circuits; phase noise; thin-film inductors; wafer-scale integration; voltage-controlled oscillators},
    number = {8},
    pages = {1280--1292},
    peerreviewed = {Yes},
    title = {High-Q Inductors Embedded in the Fan-Out Area of an eWLB},
    volume = {2},
    }

2010

  • M. Wojnowski, V. Issakov, G. Sommer, and R. Weigel, "Multimode TRL technique for de-embedding of differential devices" in 75th ARFTG Microwave Measurements Conference (ARFTG), Anaheim, CA, 2010, pp. 1-10. [DOI] [Bibtex]
    @inproceedings{wojnowski2010,
    abstract = {The thru-reflect-line (TRL) is one of the most fundamental and accurate vector network analyzer (VNA) calibration techniques. The multimode TRL calibration method generalizes the standard TRL technique to multimode waveguides. In this paper, the practical use of the multimode TRL calibration technique for de-embedding purposes is discussed. The focus is on the four-port case, since this covers the majority of the practical applications. However, the formulation can be easily extended for networks with higher number of ports. The common de-embedding assumptions such as reciprocity and symmetry are analyzed and their consequences on the multimode TRL algorithm are discussed. It is shown that the reciprocity assumption applied to the embedding networks reduces the requirements on the reflect standard. It is demonstrated that additional assumptions of either identical or symmetrical error networks make it possible to completely resolve the problem related to the reflect standard. Based on the derived formulation, it is shown that the multimode TRL calibration reduces to the traditional TRL de-embedding under reciprocity and symmetry assumptions. The problems of interpretation and re-normalization of the obtained scattering parameters (S-parameters) are also discussed. Finally, the measurement results are presented that verify the multimode TRL approach for de-embedding of four-port differential devices.},
    author = {Wojnowski, Maciej and Issakov, Vadim and Sommer, Grit and Weigel, Robert},
    booktitle = {75th ARFTG Microwave Measurements Conference (ARFTG)},
    cris = {https://cris.fau.de/converis/publicweb/publication/122339844},
    year = {2010},
    month = {05},
    doi = {10.1109/ARFTG.2010.5496326},
    faupublication = {yes},
    keywords = {Calibration; de-embedding; differentail devices; microwave measurements; scattering parameters},
    pages = {1--10},
    peerreviewed = {unknown},
    title = {Multimode TRL technique for de-embedding of differential devices},
    venue = {Anaheim, CA},
    }

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