Mitarbeiter

M. Sc. Markus Stadelmayer

Kontakt

Über Markus Stadelmayer

Lebenslauf

Markus Stadelmayer hat 2017 sein Studium der Elektrotechnik, Elektronik und Informationstechnik an der Friedrich-Alexander-Universität Erlangen-Nürnberg abgeschlossen. In seiner Masterarbeit befasste er sich mit dem Entwurf eines Pipeline Analog-Digital Umsetzers mit Kalibrationsalgorithmus. Seit 2017 arbeit er als wissenschalftlicher Mitarbeiter am Institut für integrierte Schaltungen der JKU Linz an seiner Dissertation. Zur Zeit ist er als Gastwissenschlaftler am Lehrstuhl für Technische Elektronik tätig. Sein Forschungsbereich befasst sich mit dem Entwurf von integrierten Ultra-Low-Power Sendern.

Arbeitsgebiete

  • Ultra-Low-Power RFICs
  • Mixed-Signal ICs

Abschlussarbeiten

Bitte melden, falls Interesse an einem der genannten Arbeitsgebiete besteht.

Publikationen

2019

  • J. Potschka, C. Söll, J. Kirchner, C. Mardin, M. Stadelmayer, T. Maiwald, S. Breun, K. Kolb, A. Bauch, M. Dietz, C. Beck, M. Völkel, A. Hagelauer, and R. Weigel, "Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process" in Engineering in Medicine and Biology Conference, Berlin, 2019. [Bibtex]
    @inproceedings{potschka2019,
    author = {Potschka, Julian and Söll, Christopher and Kirchner, Jens and Mardin, Christian and Stadelmayer, Markus and Maiwald, Tim and Breun, Sascha and Kolb, Katharina and Bauch, Andreas and Dietz, Marco and Beck, Christopher and Völkel, Matthias and Hagelauer, Amelie and Weigel, Robert},
    booktitle = {Engineering in Medicine and Biology Conference},
    cris = {https://cris.fau.de/converis/publicweb/publication/217754593},
    year = {2019},
    month = {07},
    day = {23},
    eventdate = {2019-07-23/2019-07-27},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process},
    type = {Konferenzschrift},
    venue = {Berlin},
    }
  • D. Schuklin, J. Röber, M. Stadelmayer, T. Mai, R. Weigel, and A. Hagelauer, "Highly Integrated Low Power Photomultiplier Readout ASIC Comprising Fast ADC to Be Used in the Antarctic Ice" in 2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Orlando, Florida, USA, 2019. [Bibtex]
    @inproceedings{schuklin2019,
    abstract = {After the successful launch of IceCube, the work is currently concentrated the next generation neutrino observatory at South Pole, IceCube Gen2. The neutrino detection and post processing accuracy mostly relies on used electronic hardware. The proposed highly integrated, low power photomultiplier readout ASIC is designed for function in low temperatures of Antarctic. The microchip comprises an input pre-amplifier, a clock generator and an ADC with encoder logic featuring sampling rate of 500MHz, 6bit output accuracy with a smart extension of input related resolution up to 8bit in the area of interest. It achieves the same accuracy like a standard 8bit ADC architecture but with significantly less hardware overhead and power dissipation.
    }, author = {Schuklin, Dennis and Röber, Jürgen and Stadelmayer, Markus and Mai, Timo and Weigel, Robert and Hagelauer, Amelie}, language = {English}, booktitle = {2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)}, cris = {https://cris.fau.de/converis/publicweb/publication/208580332}, year = {2019}, month = {02}, day = {20}, eventdate = {2019-01-20/2019-01-23}, faupublication = {yes}, peerreviewed = {unknown}, title = {Highly Integrated Low Power Photomultiplier Readout ASIC Comprising Fast ADC to Be Used in the Antarctic Ice}, type = {Konferenzschrift}, venue = {Orlando, Florida, USA}, }

2017

  • R. Löhr, M. Stadelmayer, J. Röber, F. Ohnhäuser, and R. Weigel, "A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter" in ECCTD, Italien, 2017. [Bibtex]
    @inproceedings{loehr2017,
    abstract = {
    High-Performance Analog-to-Digital Converter
    (ADC) have high requirements concerning sampling rate and
    linearity. Therefore a new formula is derived to determine,
    which pipeline stage dependent on the used capacitor sizes
    needs to be calibrated for the targeted linearity. Furthermore,
    a model of a 16 bit and 200MS/s pipeline ADC is described. A
    combination of a digital foreground and a digital background
    calibration is presented, which can compensate linear errors
    and achieves a DNL smaller than ±1 and a THD of -88 dB.
    }, author = {Löhr, Robert and Stadelmayer, Markus and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert}, language = {English}, publisher = {IEEE}, booktitle = {ECCTD}, cris = {https://cris.fau.de/converis/publicweb/publication/106860204}, year = {2017}, month = {07}, faupublication = {yes}, keywords = {Pipeline ADC,modeling,common mode jump,capacitor-flip-over architecture,digital calibration,foreground,background,high resolution.}, peerreviewed = {unknown}, title = {A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter}, venue = {Italien}, }

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