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M. Sc. Radu Ciocoveanu

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Über Radu Ciocoveanu

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Preise & Auszeichnungen

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, RWW Student Paper Competition, 2nd place, IEEE Radio and Wireless Week, 2019. [Bibtex]
    @prize{ciocoveanu_prize_2019,
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    booktitle = {IEEE Radio and Wireless Week},
    cris = {ciocoveanu_prize_2019},
    year = {2019},
    month = {01},
    day = {22},
    title = {RWW Student Paper Competition, 2nd place},
    type = {20773-Kleiner Preis},
    }

COPYRIGHT NOTICE: Copyright and all rights of the material above are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by the appropriate copyright. The material may not be reposted without the explicit permission of the copyright holder.

COPYRIGHT NOTICE FOR IEEE PUBLICATIONS: © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

COPYRIGHT NOTICE FOR EUMA PUBLICATIONS: © EUMA. Personal use of this material is permitted. Permission from European Microwave Association(EUMA) must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Publikationen

2019

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS" in IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Orlando, FL, USA, 2019 (to be published). [Bibtex]
    @inproceedings{ciocoveanu2019,
    abstract = {This paper presents a 60GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power (Pmax) of 15.3dBm with a competitive maximum power-added efficiency (PAEmax) of 30.5% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8V supply and the chip core size is 0.36mm x 0.35 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/204681005},
    year = {2019},
    month = {01},
    day = {20},
    eventdate = {2019-01-20/2019-01-23},
    faupublication = {yes},
    keywords = {Power Amplifier,High-Power,High-Efficiency,PD-SOI.},
    note = {unpublished},
    peerreviewed = {unknown},
    title = {A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {Orlando, FL, USA},
    }

2018

  • R. Ciocoveanu, R. Weigel, A. Hagelauer, A. Geiselbrechtinger, and V. Issakov, "5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS" in 5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS, Kyoto International Conference Center, Kyoto, Japan, Japan, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018c,
    abstract = {This paper presents a single-stage stacked Class AB power amplifier (PA) with lower complexity for fifth generation (5G) K/Ka band front-ends that has been realized in a 45nm PDSOI CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 17.3 dBm with a 39.7% maximum power-added efficiency (PAEmax) at 24 GHz. The output-referred 1-dB compression point (OP1dB) is 14.3dBm and the saturated output power varies from 15.9dBm to 17.3dBm for a frequency range from 22 GHz to 28 GHz. Furthermore, the circuit draws 40mA from a 2.9V supply and the chip core size is 0.35mm x 0.25 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Geiselbrechtinger, Angelika and Issakov, Vadim},
    language = {English},
    booktitle = {5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS},
    cris = {https://cris.fau.de/converis/publicweb/publication/203983358},
    year = {2018},
    month = {12},
    day = {15},
    eventdate = {2018-11-06/2018-11-09},
    eventtitle = {2018 Asia-Pacific Microwave Conference (APMC 2018)},
    faupublication = {yes},
    keywords = {Stacked PA; 45nm PD-SOI; 5G; High Power; High Efficiency},
    peerreviewed = {unknown},
    title = {5G mm-Wave Stacked Class AB Power Amplifier in 45 nm PD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {Kyoto International Conference Center, Kyoto, Japan, Japan},
    }
  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS" in A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS, San Diego, California, USA, USA, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018b,
    abstract = {This paper presents a wideband digitally tunable SPST switch based on the travelling-wave concept that has been realized in a 22 nm FD-SOI CMOS technology. The digital control for return loss is performed through mutual inductance switching. Small-signal measurement results show that the proposed SPST switch achieves a bandwidth of 10-110 GHz, with an insertion loss of 1.2 dB at 60 GHz and a 24 dB isolation at 60 GHz, whereas large-signal measurements show a 1-dB compression point of +7 dBm at 24 GHz. Furthermore, the 3 digital control bits allow tuning return loss center frequency by approximately 7 GHz. The chip core size is 0.12 mm x 0.15 mm.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS},
    cris = {https://cris.fau.de/converis/publicweb/publication/203983033},
    year = {2018},
    month = {11},
    day = {15},
    eventdate = {2018-10-14/2018-10-17},
    eventtitle = {2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {A Low Insertion-Loss 10-110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS},
    type = {Konferenzschrift},
    venue = {San Diego, California, USA, USA},
    }
  • R. Ciocoveanu, R. Weigel, A. Hagelauer, and V. Issakov, "Bias-switched Down-Conversion Mixer for Flicker Noise Reduction in 28-nm CMOS" in Texas Symposium on Wireless and Microwave Circuits and Systems, Waco, Texas, USA, 2018. [Bibtex]
    @inproceedings{ciocoveanu2018a,
    abstract = {This paper presents a modified Gilbert-cell mixer employing a novel biasing-scheme used to reduce the high Noise Figure, due to inherently high 1/f noise of MOS transistors. Switching the transistor from strong inversion to accumulation interferes with the self-correlation of the physical noisy process, which leads to a reduction in flicker noise. To illustrate this improvement, a comparison with a conventionally biased mixer is carried. Post-layout simulation results show that this mixer achieves a voltage conversion gain of 2.2 dB, a 1 dB compression point of 3 dBm and a 5 dB reduction in noise figure at 50 kHz, while it draws a current of 13 mA from a single 0.9 V supply. The occupied chip area is 0.5x0.94 mm². According to author’s knowledge this is the first time that bias switching technique is applied to a mixer at mm-wave frequencies.},
    author = {Ciocoveanu, Radu and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim},
    language = {English},
    booktitle = {Texas Symposium on Wireless and Microwave Circuits and Systems},
    cris = {https://cris.fau.de/converis/publicweb/publication/200465469},
    year = {2018},
    month = {07},
    day = {01},
    eventdate = {2018-04-05/2018-04-06},
    faupublication = {yes},
    peerreviewed = {unknown},
    title = {Bias-switched Down-Conversion Mixer for Flicker Noise Reduction in 28-nm CMOS},
    type = {Konferenzschrift},
    venue = {Waco, Texas, USA},
    }
  • R. Ciocoveanu, J. Rimmelspacher, R. Weigel, A. Hagelauer, and V. Issakov, "A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS" in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Anaheim, USA, 2018, pp. 19-22. [DOI] [Bibtex]
    @inproceedings{ciocoveanu2018,
    abstract = {
    This paper presents a high linearity modified Gilbert-cell mixer designed for 60-GHz applications and fabricated in a 28-nm CMOS technology. To increase the linearity of the mixer, the RF transconductance stage was removed, thereby reducing the amount of stacked transistors. We propose using a self-biasing Vth reference in the bias network to make the mixer more robust to process-voltagetemperature (PVT) variations. Measurement results show that this mixer achieves a voltage conversion gain of 4.7 dB, a 1-dB compression point of -3 dBm and a 12.3 dB noise figure, while it draws only 2 mA from a single 0.9 V supply. The occupied area on the chip is 0.35x0.68 mm2 including pads.
    }, author = {Ciocoveanu, Radu and Rimmelspacher, Johannes and Weigel, Robert and Hagelauer, Amelie and Issakov, Vadim}, language = {English}, booktitle = {Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems}, cris = {https://cris.fau.de/converis/publicweb/publication/111716704}, year = {2018}, month = {01}, day = {14}, doi = {10.1109/SIRF.2018.8304218}, eventdate = {2018-01-14/2018-01-17}, faupublication = {yes}, keywords = {Down-Conversion Mixer,High-Linearity,Low-Power,PVT Robust}, pages = {19--22}, peerreviewed = {unknown}, title = {A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS}, type = {Konferenzschrift}, venue = {Anaheim, USA}, }

COPYRIGHT NOTICE: Copyright and all rights of the material above are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by the appropriate copyright. The material may not be reposted without the explicit permission of the copyright holder.

COPYRIGHT NOTICE FOR IEEE PUBLICATIONS: © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

COPYRIGHT NOTICE FOR EUMA PUBLICATIONS: © EUMA. Personal use of this material is permitted. Permission from European Microwave Association(EUMA) must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.