Mitarbeiter

M. Sc. Robert Löhr

Kontakt

Über Robert Löhr

Lebenslauf

Robert Löhr hat im Mai 2013 sein Studium der Elektrotechnik, Elektronik und Informationstechnik an der Friedrich-Alexander-Universität Erlangen-Nürnberg mit Auszeichnung abgeschlossen. Seit November 2013 arbeitet er als wissenschaftlicher Mitarbeiter am Lehrstuhl für Technische Elektronik. Sein Forschungsschwerpunkt liegt im Bereich integrierte Analog-/Mixed-Signal Schaltungen mit Schwerpunkt Analog/Digital Umsetzung.

Arbeitsgebiete

  • Entwurf und Layout von integrierten Analog- und Mixed-Signal-Schaltungen
  • Analog/Digital Umsetzung
  • Kalibrieralgorithmen für Pipeline ADUs

Abschlussarbeiten

  • Entwurf einer Schnittstelle für High-Performance Pipeline Umsetzer

 

Lehrveranstaltungen Sommersemester 2019

  • Praktikum Analog-Digital-Umsetzer

  • Übungen zu Analog-Digital und Digital-Analog-Umsetzer

Preise & Auszeichnungen

  • M. Sporer and R. Löhr, 1. Platz Lehrevaluation Praktikum High-Performance Analog- und Umsetzer-Design, Technische Fakultät der FAU, 2015. [Bibtex]
    @prize{sporer_prize_2015a,
    abstract = {Praktikum High-Performance Analog- und Umsetzer-Design},
    author = {Sporer, Michael and Löhr, Robert},
    booktitle = {Technische Fakultät der FAU},
    cris = {sporer_prize_2015a},
    year = {2015},
    month = {03},
    day = {16},
    title = {1. Platz Lehrevaluation Praktikum High-Performance Analog- und Umsetzer-Design},
    type = {20773-Kleiner Preis},
    }

COPYRIGHT NOTICE: Copyright and all rights of the material above are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by the appropriate copyright. The material may not be reposted without the explicit permission of the copyright holder.

COPYRIGHT NOTICE FOR IEEE PUBLICATIONS: © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

COPYRIGHT NOTICE FOR EUMA PUBLICATIONS: © EUMA. Personal use of this material is permitted. Permission from European Microwave Association(EUMA) must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Publikationen

2017

  • R. Löhr, L. Bender, J. Röber, F. Ohnhäuser, and R. Weigel, "Analysis of the Settling Behavior of an External Reference Voltage Source for a 16 Bit and 200 MS/s Pipeline Analog-to-Digital Converter" in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgien, Georgia, 2017. [Bibtex]
    @inproceedings{loehr2017a,
    abstract = {
    High-Performance Analog to Digital Converter (ADC) have high requirements concerning the reference voltage source. In a small period of time the reference voltage has to settle with a high accuracy. Otherwise the linearity of the ADC degrades. In this paper the settling of an external reference voltage source is examined. Therefore optimization techniques for the signal path of the reference voltage are presented. This includes methods for reducing the external parasitic inductanceas well as design techniques for an enhanced settling curve. Under typical conditions, the achieved reference voltage source settles with an accuracy of 15 uV in less than halve a clock cycle for a 200 MS/s and 16 bits Pipeline ADC.
    }, author = {Löhr, Robert and Bender, Leon and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert}, language = {English}, booktitle = {24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, cris = {https://cris.fau.de/converis/publicweb/publication/119647484}, year = {2017}, month = {12}, day = {08}, eventdate = {2017-12-04/2017-12-08}, faupublication = {yes}, keywords = {reference voltage; settling; Pipeline ADC; external parasitic inductance; attenuation}, peerreviewed = {unknown}, title = {Analysis of the Settling Behavior of an External Reference Voltage Source for a 16 Bit and 200 MS/s Pipeline Analog-to-Digital Converter}, type = {Konferenzschrift}, venue = {Batumi, Georgien, Georgia}, }
  • R. Löhr, M. Stadelmayer, J. Röber, F. Ohnhäuser, and R. Weigel, "A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter" in ECCTD, Italien, 2017. [Bibtex]
    @inproceedings{loehr2017,
    abstract = {
    High-Performance Analog-to-Digital Converter
    (ADC) have high requirements concerning sampling rate and
    linearity. Therefore a new formula is derived to determine,
    which pipeline stage dependent on the used capacitor sizes
    needs to be calibrated for the targeted linearity. Furthermore,
    a model of a 16 bit and 200MS/s pipeline ADC is described. A
    combination of a digital foreground and a digital background
    calibration is presented, which can compensate linear errors
    and achieves a DNL smaller than ±1 and a THD of -88 dB.
    }, author = {Löhr, Robert and Stadelmayer, Markus and Röber, Jürgen and Ohnhäuser, Frank and Weigel, Robert}, language = {English}, publisher = {IEEE}, booktitle = {ECCTD}, cris = {https://cris.fau.de/converis/publicweb/publication/106860204}, year = {2017}, month = {07}, faupublication = {yes}, keywords = {Pipeline ADC,modeling,common mode jump,capacitor-flip-over architecture,digital calibration,foreground,background,high resolution.}, peerreviewed = {unknown}, title = {A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter}, venue = {Italien}, }

2016

  • R. Löhr, F. Ohnhäuser, J. Röber, and R. Weigel, "Switch Bootstrapping in a 1.5 Bit Pipeline Stage" in Analog2016, Bremen, 2016, pp. 49-52. [Bibtex]
    @inproceedings{loehr2016,
    abstract = {The targeted 16 bit pipeline converter has an adjustable sampling frequency from 100MHz to 200MHz. In this paper the switches for the input and the reference voltage sampling are analyzed. Therefore, a novel switch bootstrapping technique is presented, which guarantees a worst case input voltage settling accuracy of LSB 2 at settling times between 2 ns to 5 ns. The non-linearity caused by the input switches is simulated and typically amounts to -115 dB. In addition a possible solution for external reference voltage settling is introduced.},
    author = {Löhr, Robert and Ohnhäuser, Frank and Röber, Jürgen and Weigel, Robert},
    booktitle = {Analog2016},
    cris = {https://cris.fau.de/converis/publicweb/publication/122835064},
    year = {2016},
    eventtitle = {Analog2016},
    faupublication = {yes},
    keywords = {1.5 bit,switch bootstrapping,MDAC,charge injection,external reference,non-linearity},
    pages = {49--52},
    peerreviewed = {Yes},
    title = {Switch Bootstrapping in a 1.5 Bit Pipeline Stage},
    venue = {Bremen},
    }

2015

  • R. Löhr, M. Kempf, F. Ohnhäuser, J. Röber, R. Weigel, and A. Bänisch, "Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process" in International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Nusa Dua, Bali, 2015. [DOI] [Bibtex]
    @inproceedings{loehr2015,
    abstract = {Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.},
    author = {Löhr, Robert and Kempf, Markus and Ohnhäuser, Frank and Röber, Jürgen and Weigel, Robert and Bänisch, Andreas},
    booktitle = {International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
    cris = {https://cris.fau.de/converis/publicweb/publication/120749684},
    year = {2015},
    month = {11},
    doi = {10.1109/ISPACS.2015.7432788},
    eventtitle = {International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process},
    venue = {Nusa Dua, Bali},
    }

COPYRIGHT NOTICE: Copyright and all rights of the material above are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by the appropriate copyright. The material may not be reposted without the explicit permission of the copyright holder.

COPYRIGHT NOTICE FOR IEEE PUBLICATIONS: © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

COPYRIGHT NOTICE FOR EUMA PUBLICATIONS: © EUMA. Personal use of this material is permitted. Permission from European Microwave Association(EUMA) must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.