Mitarbeiter

M. Sc. Sascha Breun

Kontakt

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  • Telefon: 09131/85-27189
  • Fax: 09131/85-28730
  • Raum: 3.234
  • Cauerstraße 9
    91058 Erlangen

Über Sascha Breun

Lebenslauf

Sascha hat im April 2018 sein Studium der Elektrotechnik, Elektronik und Informationstechnik an der Friedrich-Alexander-Universität Erlangen-Nürnberg mit Auszeichnung abgeschlossen. Seit Juli 2018 arbeitet er als wissenschaftlicher Mitarbeiter am Lehrstuhl für Technische Elektronik. Sein Forschungsbereich liegt dabei im Bereich RF-Chipdesign.

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Publikationen

2020

  • S. Breun, S. Kehl-Waas, and V. Issakov, "Extended Equivalent Circuit Model for Enhanced Substrate Modeling of Three-Port Inductors" in RWW 2020, 2020 (to be published). [Bibtex]
    @inproceedings{breun2020,
    abstract = {This paper presents an extension to the equivalent circuit of a three-port inductor model which enhances the quality factor accuracy by precisely considering the parasitic substrate losses caused by eddy current effects. The proposed equivalent circuit allows to correctly model the broadband frequency dependency of the substrate admittances. Furthermore it is applied to an almost fully analytical extraction procedure and can therefore be used for the generation of scalable inductor models.
    }, author = {Breun, Sascha and Kehl-Waas, Sebastian and Issakov, Vadim}, language = {English}, booktitle = {RWW 2020}, cris = {https://cris.fau.de/converis/publicweb/publication/227024935}, year = {2020}, month = {01}, day = {26}, eventdate = {2020-01-26/2020-01-29}, faupublication = {yes}, note = {unpublished}, peerreviewed = {automatic}, title = {Extended Equivalent Circuit Model for Enhanced Substrate Modeling of Three-Port Inductors}, }
  • S. Breun, M. Völkel, A. Schrotz, M. Dietz, V. Issakov, and R. Weigel, "A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with -178 dBc/Hz FOMT" in RWW 2020, 2020 (to be published). [Bibtex]
    @inproceedings{breun2020a,
    abstract = {This paper presents a low-power wideband push-push voltage controlled oscillator (VCO), achieving a frequency tuning-range (FTR) of 19 GHz (14 %) at a center frequency of 136 GHz. The VCO yields a minimum phase noise of −86.5 dBc/Hz at 1 MHz offset at a power consumption of around 27 mW from a 1.8 V supply, which yields a FOMT of −178 dBc/Hz. The chip is fabricated using a 130 nm SiGe BiCMOS technology with ft/fmax of 250 GHz/370 GHz, respectively, and is integrated with a by-32 divider chain attached to the fundamental output of the VCO, offering a 2.1 GHz output for an external phaselocked loop (PLL).
    }, author = {Breun, Sascha and Völkel, Matthias and Schrotz, Albert-Marcel and Dietz, Marco and Issakov, Vadim and Weigel, Robert}, language = {English}, booktitle = {RWW 2020}, cris = {https://cris.fau.de/converis/publicweb/publication/227024522}, year = {2020}, month = {01}, day = {26}, eventdate = {2020-01-26/2020-01-29}, faupublication = {yes}, note = {unpublished}, peerreviewed = {automatic}, title = {A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with -178 dBc/Hz FOMT}, }

2019

  • J. Potschka, M. Dietz, K. Kolb, T. Maiwald, S. Breun, T. Ackermann, D. Ferling, A. Hagelauer, and R. Weigel, "A Highly Linear and Efficient 28 GHz Stacked Power Amplifier for 5G using Analog Predistortion in a 130 nm BiCMOS Process (to be published)" in IEEE Asia-Pacific Microwave Conference (APMC), Singapore, 2019. [Bibtex]
    @inproceedings{potschka2019a,
    author = {Potschka, Julian and Dietz, Marco and Kolb, Katharina and Maiwald, Tim and Breun, Sascha and Ackermann, Thomas and Ferling, Dieter and Hagelauer, Amelie and Weigel, Robert},
    language = {English},
    booktitle = {IEEE Asia-Pacific Microwave Conference (APMC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/225496208},
    year = {2019},
    month = {12},
    day = {10},
    eventdate = {2019-12-10/2019-12-13},
    faupublication = {yes},
    keywords = {Analog Predistortion; Power Amplifier; 5G},
    peerreviewed = {Yes},
    title = {A Highly Linear and Efficient 28 GHz Stacked Power Amplifier for 5G using Analog Predistortion in a 130 nm BiCMOS Process (to be published)},
    type = {Konferenzschrift},
    venue = {Singapore},
    }
  • A. Schrotz, T. Maiwald, K. Kolb, S. Breun, M. Dietz, A. Hagelauer, and R. Weigel, "Design Methodology for Automatically Designed, Integrated Marchand Baluns with Low Insertion Loss at Lowest Phase Imbalance" in APMC (Asia-Pacific Microwave Conference), Singapur, Singapore, 2019 (to be published). [Bibtex]
    @inproceedings{schrotz2019,
    abstract = {In this paper, a design methodology for automated Marchand balun design is shown. The goal of this methodology is a balun providing the lowest insertion loss at the smallest phase imbalance. The design process is realized by using the EM simulator Sonnet, Matlab and the Matlab-Sonnet interface. The implemented algorithm is using a simulation-based characterization of the semiconductor process and a mathematical model of the balun. For this characterization an even and odd mode analysis is carried out. Hence, the electrical and dielectric properties, such as the characteristic impedance and the effective permittivity, are determined. This enables a precise "first guess simulation" of the balun, minimizing the required number of optimization iterations. As an example, a D-band Marchand balun is presented here, that was designed with this methodology. The measurement results show a phase imbalance less than 7° over the entire D-band and an insertion loss smaller than 1.75 dB. To the best of the author's knowledge, there was no software tool that enables automated development for Marchand baluns yet, although it is widely used.
    }, author = {Schrotz, Albert-Marcel and Maiwald, Tim and Kolb, Katharina and Breun, Sascha and Dietz, Marco and Hagelauer, Amelie and Weigel, Robert}, language = {English}, booktitle = {APMC (Asia-Pacific Microwave Conference)}, cris = {https://cris.fau.de/converis/publicweb/publication/224804429}, year = {2019}, month = {12}, day = {10}, eventdate = {2019-12-10}, faupublication = {yes}, keywords = {Marchand Balun; Automatically balun Design}, note = {unpublished}, peerreviewed = {automatic}, title = {Design Methodology for Automatically Designed, Integrated Marchand Baluns with Low Insertion Loss at Lowest Phase Imbalance}, venue = {Singapur, Singapore}, }
  • M. Völkel, M. Thouabtia, S. Breun, K. Aufinger, R. Weigel, and A. Hagelauer, "A Signal Source Chip at 140 GHz and 160 GHz for Radar Applications in a SiGe Bipolar Technology" in MWSCAS, Dallas, USA, 2019. [Bibtex]
    @inproceedings{voelkel2019d,
    abstract = {In this paper, a monolithic signal source chip at
    140 GHz and 160 GHz including two VCOs, a dynamic divider
    and a static divider chain is presented. Two signal sources with
    these high fundamental frequencies are realized. All components
    have been designed using a 0.13μm 250 GHz fT SiGe BiCMOS
    technology. The whole integrated circuit has a size of 930μm
    x 600μm including bondpads and consumes 210mA from a
    3.3V and 130mA from a 1.8V supply. The oscillators cover
    a frequency range from 119.3–147.7 GHz and 154.2–164 GHz,
    which results in a tuning range of 28.4 GHz and 9.8 GHz. A
    output power of -0.9/3.6dBm with a best case phase noise of
    -111.2/-108 dBc/Hz at 1MHz offset, measured at the divider
    output for PLL stabilization is achieved.
    }, author = {Völkel, Matthias and Thouabtia, Mohamed and Breun, Sascha and Aufinger, Klaus and Weigel, Robert and Hagelauer, Amelie}, language = {English}, booktitle = {MWSCAS}, cris = {https://cris.fau.de/converis/publicweb/publication/217336772}, year = {2019}, month = {08}, day = {05}, eventdate = {2019-08-04/2019-08-07}, faupublication = {yes}, keywords = {FMCW; industrial radar; millimeter-wave; oscillator; signal source; VCO.}, peerreviewed = {unknown}, title = {A Signal Source Chip at 140 GHz and 160 GHz for Radar Applications in a SiGe Bipolar Technology}, type = {Konferenzschrift}, venue = {Dallas, USA}, }
  • J. Potschka, C. Söll, J. Kirchner, C. Mardin, M. Stadelmayer, T. Maiwald, S. Breun, K. Kolb, A. Bauch, M. Dietz, C. Beck, M. Völkel, A. Hagelauer, and R. Weigel, "Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process" in IEEE Engineering in Medicine and Biology Conference (EMBC), Berlin, 2019. [Bibtex]
    @inproceedings{potschka2019,
    author = {Potschka, Julian and Söll, Christopher and Kirchner, Jens and Mardin, Christian and Stadelmayer, Markus and Maiwald, Tim and Breun, Sascha and Kolb, Katharina and Bauch, Andreas and Dietz, Marco and Beck, Christopher and Völkel, Matthias and Hagelauer, Amelie and Weigel, Robert},
    booktitle = {IEEE Engineering in Medicine and Biology Conference (EMBC)},
    cris = {https://cris.fau.de/converis/publicweb/publication/217754593},
    year = {2019},
    month = {07},
    day = {23},
    eventdate = {2019-07-23/2019-07-27},
    faupublication = {yes},
    peerreviewed = {Yes},
    title = {Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process},
    type = {Konferenzschrift},
    venue = {Berlin},
    }
  • V. Issakov, S. Kehl-Waas, and S. Breun, "Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors", IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 66, iss. 9, pp. 3557-3570, 2019. [DOI] [Bibtex]
    @article{issakov2019a,
    abstract = {This paper presents a new, almost fully analytical methodology for component value extraction of a double-π equivalent circuit model for three-port on-chip inductors from a given S-parameter dataset. The compact model provides an accurate fit over a wide frequency range from dc to beyond the self-resonance frequency (SRF) to a tabular input S-parameter model describing a symmetric center-tapped on-chip inductor. The input dataset may be obtained from a measurement or from an electromagnetic field solver simulation. Using a passive broadband equivalent circuit instead of the original S-parameters' description is advantageous for circuit design, as it facilitates the convergence of transient simulations. The proposed approach carefully considers center-tap parasitics. Hence, the obtained equivalent circuit model fits the input inductor characteristics accurately not only for differential excitation but also in the common-mode and single-ended operation. Due to the fact that the proposed extraction approach is based on physical assumptions and analytical circuit decomposition, the obtained component values are physically meaningful and relate to geometry. Thus, this approach is suitable for the generation of scalable compact models, which can be used to speed-up inductor optimization during the RF circuit design. The proposed methodology has been verified on a three-port inductor realized in a 28-nm CMOS technology and measured up to 60 GHz. The extracted equivalent circuit model exhibits an accurate fit to the measured data over the entire frequency range in all operation modes. Finally, field-solver models are used to verify the scalability.
    }, author = {Issakov, Vadim and Kehl-Waas, Sebastian and Breun, Sascha}, cris = {https://cris.fau.de/converis/publicweb/publication/227025706}, year = {2019}, doi = {10.1109/TCSI.2019.2926737}, faupublication = {yes}, issn = {1549-8328}, journaltitle = {IEEE Transactions on Circuits and Systems I-Regular Papers}, keywords = {circuit optimisation;CMOS integrated circuits;equivalent circuits;inductors;integrated circuit modelling;multiport networks;network analysis;radiofrequency integrated circuits;S-parameters;input inductor characteristics;analytical circuit decomposition;analytical equivalent circuit extraction procedure;component value extraction;double-π equivalent circuit model;self-resonance frequency;symmetric center-tapped on-chip inductor;passive broadband equivalent circuit;center-tap parasitics;Broadband Scalable Modeling;three-port center-tapped symmetric on-chip inductors;S-parameter dataset;electromagnetic field solver simulation;single-ended operation;common-mode operation;transient simulations;CMOS technology;Integrated circuit modeling;Inductors;Equivalent circuits;Analytical models;Scattering parameters;Geometry;Numerical models;Equivalent circuit;on-chip inductor;center-tap}, number = {9}, pages = {3557--3570}, peerreviewed = {Yes}, shortjournal = {IEEE T CIRCUITS-I}, title = {Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors}, volume = {66}, }

2018

  • J. Rimmelspacher, S. Breun, A. Werthof, A. Geiselbrechtinger, R. Weigel, and V. Issakov, "Experimental Comparison of Integrated Transformers in a 28 nm Bulk CMOS Technology" in European Microwave Conference 2018, Madrid, Spain, 2018. [Bibtex]
    @inproceedings{rimmelspacher2018b,
    abstract = {This paper presents a systematic comparison of integrated transformer structures realized in a 28 nm bulk CMOS technology and characterized up to the millimetre-wave frequencies. First, the rectangular versus octagonal coil shapes are compared. Next, different transformer routing realizations using various magnetic coupling mechanisms are examined: interleaved transformers using lateral coupling, stacked ones using vertical coupling and symmetrical transformers using the combination of both coupling mechanisms. Finally, the comparison is repeated for different turn ratios: 1:1, 1:2 and 2:2. The electrical properties of the transformers, such as self-inductance, quality factor, self-resonance frequencies and mutual coupling coefficient are analysed. Advantages and disadvantages of these structures are discussed with regard to their applicability in various active circuits. One of the main targets is to obtain the best transformer’s electrical parameters for a given fixed area and given metallization option. The structures are measured up to 70 GHz. On-chip interconnects are de-embedded and the devices are compared to the models simulated by EM field solver.
    }, author = {Rimmelspacher, Johannes and Breun, Sascha and Werthof, Andreas and Geiselbrechtinger, Angelika and Weigel, Robert and Issakov, Vadim}, booktitle = {European Microwave Conference 2018}, cris = {https://cris.fau.de/converis/publicweb/publication/200127203}, year = {2018}, month = {09}, day = {25}, eventdate = {2018-09-25/2018-09-27}, faupublication = {no}, keywords = {millimeter-wave,CMOS,transformers}, peerreviewed = {unknown}, title = {Experimental Comparison of Integrated Transformers in a 28 nm Bulk CMOS Technology}, type = {Konferenzschrift}, venue = {Madrid, Spain}, }
  • M. Hertlein, S. Breun, G. Cappel, A. Schwarzmeier, F. Lurz, R. Weigel, and G. Fischer, "Evaluation of Cellular Standards for Low Data Rate Applications Regarding Power Consumption and Timing Parameters" in IEEE Radio Wireless Symposium, Anaheim, CA, USA, 2018, pp. 217-219. [DOI] [Bibtex]
    @inproceedings{hertlein2018,
    abstract = {3GPP introduced new specifications for low data rate applications, due to the IoT sector and also the enormous amount of connected devices. This standards should reduce overhead, increase coverage and reduce power consumption in addition to an increasing capacity. This paper focuses on power consumption measurements of the current existing standards e.g. LTE and makes a comparison with the new Narrowband-IoT standards. Also an evaluation on timing parameters and different modes during the transmission is given. Finally this paper helps to decide which standard provides the best benefit for a certain application.},
    author = {Hertlein, Markus and Breun, Sascha and Cappel, Germar and Schwarzmeier, Andre and Lurz, Fabian and Weigel, Robert and Fischer, Georg},
    language = {English},
    booktitle = {IEEE Radio Wireless Symposium},
    cris = {https://cris.fau.de/converis/publicweb/publication/111580524},
    year = {2018},
    month = {01},
    day = {14},
    doi = {10.1109/RWS.2018.8304991},
    eventdate = {2018-01-14/2018-01-17},
    faupublication = {yes},
    keywords = {Cellular networks,Internet of Things (IoT),Narrowband IoT,Power consumption},
    pages = {217--219},
    peerreviewed = {unknown},
    title = {Evaluation of Cellular Standards for Low Data Rate Applications Regarding Power Consumption and Timing Parameters},
    type = {Konferenzschrift},
    url = {https://ieeexplore.ieee.org/document/8304991/},
    venue = {Anaheim, CA, USA},
    }

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